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1. 发明授权

US08621409B2 System and method for reducing layout-dependent effects 有权
标题翻译：减少与布局有关的影响的系统和方法
公开(公告)号：US08621409B2
公开(公告)日：2013-12-31
申请号：US13459288
申请日：2012-04-30
申请人： Hui Yu Lee , Feng Wei Kuo , Ching-Shun Yang , Yi-Kan Cheng , Jui-Feng Kuan
发明人： Hui Yu Lee , Feng Wei Kuo , Ching-Shun Yang , Yi-Kan Cheng , Jui-Feng Kuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.
摘要翻译：一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。第二布局存储在非瞬态存储介质中。

2. 发明授权

US08453095B2 Systems and methods for creating frequency-dependent netlist 有权
标题翻译：用于创建频率相关网表的系统和方法
公开(公告)号：US08453095B2
公开(公告)日：2013-05-28
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

3. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

4. 发明授权

US08495532B2 Systems and methods for creating frequency-dependent RC extraction netlist 有权
标题翻译：用于创建频率依赖的RC提取网表的系统和方法
公开(公告)号：US08495532B2
公开(公告)日：2013-07-23
申请号：US13076649
申请日：2011-03-31
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
摘要翻译：一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

5. 发明申请

US20120054696A1 Mask-Shift-Aware RC Extraction for Double Patterning Design 有权
标题翻译：双面图案设计的Mask-Shift-Aware RC提取
公开(公告)号：US20120054696A1
公开(公告)日：2012-03-01
申请号：US13167905
申请日：2011-06-24
申请人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

6. 发明授权

US08601416B2 Method of circuit design yield analysis 有权
标题翻译：电路设计产量分析方法
公开(公告)号：US08601416B2
公开(公告)日：2013-12-03
申请号：US13535709
申请日：2012-06-28
申请人： Chin-Cheng Kuo , Wei-Yi Hu , Jui-Feng Kuan , Yi-Kan Cheng
发明人： Chin-Cheng Kuo , Wei-Yi Hu , Jui-Feng Kuan , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.
摘要翻译：一种方法包括（a）产生一组样本，每个样本表示相应的一组半导体制造工艺变化值; （b）基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; （c）在不执行蒙特卡罗模拟的情况下，基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及（d）如果估计的收益率测量低于规格收益率值，则输出设计修改适当的指示。

7. 发明授权

US08252489B2 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08252489B2
公开(公告)日：2012-08-28
申请号：US13167905
申请日：2011-06-24
申请人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

8. 发明授权

US08707245B2 Semiconductor device design method, system and computer-readable medium 有权
标题翻译：半导体器件设计方法，系统和计算机可读介质
公开(公告)号：US08707245B2
公开(公告)日：2014-04-22
申请号：US13406108
申请日：2012-02-27
申请人： Ching-Shun Yang , Ze-Ming Wu , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ching-Shun Yang , Ze-Ming Wu , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5081 , G03F7/00 , G06F17/5036 , G06F2217/82
摘要： In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，从半导体器件的布局中提取第一和第二电子部件。半导体器件具有半导体衬底和半导体衬底中的第一和第二电子部件。使用第一工具提取第一和第二电气部件之间的半导体衬底中的耦合的寄生参数。使用与第一工具不同的第二工具提取第一和第二电气部件的固有参数。提取的寄生参数和固有参数被组合成半导体器件的模型。基于包括在第二工具中的耦合模型，提取耦合的寄生参数。

9. 发明授权

US08694938B2 Discrete device modeling 有权
标题翻译：离散设备建模
公开(公告)号：US08694938B2
公开(公告)日：2014-04-08
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

10. 发明申请

US20140007028A1 DISCRETE DEVICE MODELING 有权
标题翻译：离散装置建模
公开(公告)号：US20140007028A1
公开(公告)日：2014-01-02
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

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