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1. 发明申请

US20120260225A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大型集成电路的精确寄生电容提取
公开(公告)号：US20120260225A1
公开(公告)日：2012-10-11
申请号：US13527096
申请日：2012-06-19
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

2. 发明授权

US08119310B1 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08119310B1
公开(公告)日：2012-02-21
申请号：US12872938
申请日：2010-08-31
申请人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
发明人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/70
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

3. 发明申请

US20090007035A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大型集成电路的精确寄生电容提取
公开(公告)号：US20090007035A1
公开(公告)日：2009-01-01
申请号：US11865304
申请日：2007-10-01
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

4. 发明申请

US20070266360A1 Metal Thickness Simulation for Improving RC Extraction Accuracy 审中-公开
标题翻译：提高RC提取精度的金属厚度模拟
公开(公告)号：US20070266360A1
公开(公告)日：2007-11-15
申请号：US11688692
申请日：2007-03-20
申请人： Yi-Kan Cheng , Ke-Ying Su , Victor C. Y. Chang
发明人： Yi-Kan Cheng , Ke-Ying Su , Victor C. Y. Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout, generating a dielectric thickness and a metal thickness on one of the plurality of grids; extracting a capacitance based on the dielectric thickness on the one of the plurality of grids; and extracting a resistance based on the metal thickness on the one of the plurality of grids.
摘要翻译：集成电路（IC）设计方法包括提供在多个网格中定义的设计布局; 模拟化学机械抛光（CMP）工艺到具有由设计布局限定的图案化结构的IC衬底，在所述多个栅格之一上产生电介质厚度和金属厚度; 基于所述多个栅格中的所述一个栅极上的电介质厚度提取电容; 以及基于所述多个网格中的所述一个网格上的金属厚度提取电阻。

5. 发明申请

US20070266356A1 IC Design Flow Enhancement With CMP Simulation 有权
标题翻译： IC设计流程增强与CMP模拟
公开(公告)号：US20070266356A1
公开(公告)日：2007-11-15
申请号：US11688654
申请日：2007-03-20
申请人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
发明人： Gwan Sin Chang , Yi-Kan Cheng , Ivy Chiu , Ke-Ying Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5031 , G06F2217/12 , Y02P90/265
摘要： An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.
摘要翻译：集成电路（IC）设计方法包括提供IC设计布局数据; 基于IC设计布局模拟化学机械抛光（CMP）工艺到材料层，以产生各种几何参数; 根据CMP工艺仿真的各种几何参数提取电阻和电容; 并且基于所提取的电阻和电容来执行电路定时分析。

6. 发明授权

US08751975B2 RC corner solutions for double patterning technology 有权
标题翻译：用于双重图案化技术的RC角解决方案
公开(公告)号：US08751975B2
公开(公告)日：2014-06-10
申请号：US13479076
申请日：2012-05-23
申请人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.
摘要翻译：一种方法包括确定用于形成集成电路的模型参数，以及使用模型参数生成技术文件。该技术文件包括C_worst表，C_best表和C_nominal表中的至少两个。当包括布局图案的光刻掩模相对于彼此移动时，C_worst表存储集成电路的布局图案之间的最大寄生电容。当光刻掩模相对于彼此移动时，C_best表存储布局图案之间的最小寄生电容。当光刻掩模不相对于彼此移动时，C_nominal表存储布局图案之间的标称寄生电容。该技术文件体现在有形的非暂时性存储介质上。

7. 发明申请

US20130139121A1 RC Extraction Methodology for Floating Silicon Substrate with TSV 有权
标题翻译：具有TSV的浮动硅衬底的RC提取方法
公开(公告)号：US20130139121A1
公开(公告)日：2013-05-30
申请号：US13366756
申请日：2012-02-06
申请人： Ze-Ming Wu , Ching-Shun Yang , Ke-Ying Su , Hsiao-Shu Chao
发明人： Ze-Ming Wu , Ching-Shun Yang , Ke-Ying Su , Hsiao-Shu Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068
摘要： The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.
摘要翻译：本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。在一些实施例中，子电路耦合到模型的浮动公共节点。浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，由此提供在GDS和APR流之间一致的插入器晶片模型。

8. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

9. 发明授权

US08214784B2 Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确寄生电容提取
公开(公告)号：US08214784B2
公开(公告)日：2012-07-03
申请号：US12893870
申请日：2010-09-29
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

10. 发明授权

US08887106B2 Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process 有权
标题翻译：产生导电特征的偏置调整布局设计的方法和产生预定制造工艺的仿真模型的方法
公开(公告)号：US08887106B2
公开(公告)日：2014-11-11
申请号：US13370994
申请日：2012-02-10
申请人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70 , G03F7/70433 , G03F7/70441 , G06F17/5072
摘要： A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.
摘要翻译：产生导电特征的偏置调节布局设计的方法包括接收导电特征的布局设计。如果布局设计的几何配置在预定标准的第一组内，则根据第一布局偏置规则产生导电特征的偏置调整布局设计。如果布局设计的几何结构在预定标准的第二组内，则根据第二布局偏差规则产生导电特征的偏置调节布局设计。

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