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1. 发明授权

US08495532B2 Systems and methods for creating frequency-dependent RC extraction netlist 有权
标题翻译：用于创建频率依赖的RC提取网表的系统和方法
公开(公告)号：US08495532B2
公开(公告)日：2013-07-23
申请号：US13076649
申请日：2011-03-31
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
摘要翻译：一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

2. 发明授权

US08468470B2 Multi-patterning method 有权
标题翻译：多图案化方法
公开(公告)号：US08468470B2
公开(公告)日：2013-06-18
申请号：US13238127
申请日：2011-09-21
申请人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.
摘要翻译：一种方法包括（a）接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据，该布局包括通过多图案化工艺在DPT层中形成的多个多边形; （b）使用彼此相同的光掩模来接收要在DPT层中形成的多个多边形的子集的至少一个标识; （c）构造所述多个多边形的子集的图形和所述多个多边形中的任何中间多边形，其中所述多个多边形的所述子集由所述图形中的单个节点表示，所述图包括连接相邻的多边形的连接图中的多边形位于彼此的阈值距离内; 和（d）如果连接的任何子集形成奇数循环，则识别多图案化冲突。

3. 发明授权

US08448120B2 RC extraction for single patterning spacer technique 有权
标题翻译： RC提取单图案间隔技术
公开(公告)号：US08448120B2
公开(公告)日：2013-05-21
申请号：US13045839
申请日：2011-05-09
申请人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50 , G03F1/36 , G03F1/38 , G06F17/5081 , G06F2217/84 , H01L27/0207
摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.
摘要翻译：一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

4. 发明申请

US20120288786A1 RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE 有权
标题翻译： RC提取单模式间距技术
公开(公告)号：US20120288786A1
公开(公告)日：2012-11-15
申请号：US13045839
申请日：2011-05-09
申请人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F1/00 , G06F17/50 , G03F7/20
CPC分类号： G06F17/50 , G03F1/36 , G03F1/38 , G06F17/5081 , G06F2217/84 , H01L27/0207
摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.
摘要翻译：一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

5. 发明申请

US20120254811A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT RC EXTRACTION NETLIST 有权
标题翻译：用于创建频率依赖性RC提取网络列表的系统和方法
公开(公告)号：US20120254811A1
公开(公告)日：2012-10-04
申请号：US13076649
申请日：2011-03-31
申请人： Ke-Ying SU , Ching-Shun YANG , Jui-Feng KUAN , Hsiao-Shu CHAO , Yi-Kan CHENG
发明人： Ke-Ying SU , Ching-Shun YANG , Jui-Feng KUAN , Hsiao-Shu CHAO , Yi-Kan CHENG
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
摘要翻译：一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

6. 发明申请

US20120226479A1 Method of Generating RC Technology File 有权
标题翻译：生成RC技术文件的方法
公开(公告)号：US20120226479A1
公开(公告)日：2012-09-06
申请号：US13039730
申请日：2011-03-03
申请人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.
摘要翻译：公开了一种产生电阻 - 电容（RC）技术文件的方法。该方法包括从IC铸造接收多个金属方案并将多个金属方案分成一个或多个模块化RC组。该方法还包括识别模块化RC结构; 通过场解算器计算模块RC结构的电容值; 基于不具有互连的各种互连层计算RC结构的等效介电常数和等效高度; 计算所述多个金属方案中的每一种的等效介电常数和等效高度; 以及从所述模块化RC结构的电容值导出所述多个金属方案中的每一个的电容值。

7. 发明授权

US08252489B2 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08252489B2
公开(公告)日：2012-08-28
申请号：US13167905
申请日：2011-06-24
申请人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

8. 发明申请

US20120210279A1 DECOMPOSITION AND MARKING OF SEMICONDUCTOR DEVICE DESIGN LAYOUT IN DOUBLE PATTERNING LITHOGRAPHY 有权
标题翻译：半导体器件的分解和标记设计设计布局在双向图案中
公开(公告)号：US20120210279A1
公开(公告)日：2012-08-16
申请号：US13027520
申请日：2011-02-15
申请人： Chin-Chang HSU , Wen-Ju YANG , Hsiao-Shu CHAO , Yi-Kan CHENG , Lee-Chung LU
发明人： Chin-Chang HSU , Wen-Ju YANG , Hsiao-Shu CHAO , Yi-Kan CHENG , Lee-Chung LU
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.
摘要翻译：提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层特征。

9. 发明授权

US08201111B2 Table-based DFM for accurate post-layout analysis 有权
标题翻译：基于表的DFM，用于精确的布局后分析
公开(公告)号：US08201111B2
公开(公告)日：2012-06-12
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

10. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

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