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1. 发明授权

US08453095B2 Systems and methods for creating frequency-dependent netlist 有权
标题翻译：用于创建频率相关网表的系统和方法
公开(公告)号：US08453095B2
公开(公告)日：2013-05-28
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

2. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

3. 发明授权

US08448100B1 Tool and method for eliminating multi-patterning conflicts 有权
标题翻译：消除多图案化冲突的工具和方法
公开(公告)号：US08448100B1
公开(公告)日：2013-05-21
申请号：US13444158
申请日：2012-04-11
申请人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
发明人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.
摘要翻译：计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

4. 发明申请

US20110072405A1 Chip-Level ECO Shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US20110072405A1
公开(公告)日：2011-03-24
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

5. 发明授权

US08418117B2 Chip-level ECO shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US08418117B2
公开(公告)日：2013-04-09
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

6. 发明授权

US08601408B2 Method and system for replacing a pattern in a layout 有权
公开(公告)号：US08601408B2
公开(公告)日：2013-12-03
申请号：US13269757
申请日：2011-10-10
申请人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
发明人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

7. 发明授权

US08907441B2 Methods for double-patterning-compliant standard cell design 有权
标题翻译：符合双重图案的标准电池设计方法
公开(公告)号：US08907441B2
公开(公告)日：2014-12-09
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L21/70 , H01L27/02 , H01L23/528 , H01L27/118
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

8. 发明申请

US20110119648A1 ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY 有权
标题翻译：双文件技术的路由系统和方法
公开(公告)号：US20110119648A1
公开(公告)日：2011-05-19
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

9. 发明申请

US20110193234A1 Methods for Double-Patterning-Compliant Standard Cell Design 有权
标题翻译：双图案化标准单元设计方法
公开(公告)号：US20110193234A1
公开(公告)日：2011-08-11
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

10. 发明授权

US08239806B2 Routing system and method for double patterning technology 有权
标题翻译：双重图案化技术的路由系统和方法
公开(公告)号：US08239806B2
公开(公告)日：2012-08-07
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

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