专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07438822B2 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US07438822B2
公开(公告)日：2008-10-21
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
发明人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
IPC分类号： C23F1/00
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

2. 发明申请

US20060037940A1 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US20060037940A1
公开(公告)日：2006-02-23
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
发明人： Hongwen Yan , Brian Ji , Siddhartha Panda , Richard Wise , Bomy Chen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

3. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

4. 发明申请

US20070056930A1 POLYSILICON ETCHING METHODS 审中-公开
标题翻译：多晶硅蚀刻方法
公开(公告)号：US20070056930A1
公开(公告)日：2007-03-15
申请号：US11162550
申请日：2005-09-14
申请人： Seiji Iseda , Siddhartha Panda , Michael Sievers , Richard Wise
发明人： Seiji Iseda , Siddhartha Panda , Michael Sievers , Richard Wise
IPC分类号： C03C25/68 , B44C1/22 , H01L21/461 , C23F1/00
CPC分类号： H01L21/32137
摘要： Polysilicon etching methods are disclosed that employ a gas flow including perfluorocyclopentene (C5F8) and nitrogen trifluoride (NF3). The etching methods achieved a substantially vertical profile and smoother surfaces, and may achieve a 3sigma variation as low as 3.0 nm.
摘要翻译：公开了采用包括全氟环戊烯（C 5 H 5 F 8 N）和三氟化氮（NF 3 3））的气流的多晶硅蚀刻方法。蚀刻方法实现了基本垂直的轮廓和更平滑的表面，并且可以实现低至3.0nm的3σ变化。

5. 发明授权

US07754615B2 Method and apparatus for detecting endpoint in a dry etching system by monitoring a superimposed DC current 失效
标题翻译：通过监测叠加的直流电流来检测干蚀刻系统中的端点的方法和装置
公开(公告)号：US07754615B2
公开(公告)日：2010-07-13
申请号：US11495725
申请日：2006-07-31
申请人： Siddhartha Panda , Richard Wise , Lee Chen , Michael Sievers
发明人： Siddhartha Panda , Richard Wise , Lee Chen , Michael Sievers
IPC分类号： H01L21/302
CPC分类号： H01J37/32935 , H01J37/32963 , H01L22/26
摘要： A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron/ion flux to exposed surfaces, the electron temperature, etc.
摘要翻译：描述了一种用于检测干等离子体蚀刻系统中的端点的方法和装置，其包括第一电极（例如，上电极）和第二电极（例如下电极），基板搁置在该第二电极上。在第一电极和围绕第二电极的环形电极之间施加直流（DC）电压，并且监视直流电流以确定蚀刻工艺的终点。直流电流受等离子体的阻抗影响，因此响应于许多变化，包括例如等离子体密度，暴露表面的电子/离子通量，电子温度等。

6. 发明授权

US07288482B2 Silicon nitride etching methods 有权
标题翻译：氮化硅蚀刻方法
公开(公告)号：US07288482B2
公开(公告)日：2007-10-30
申请号：US10908252
申请日：2005-05-04
申请人： Siddhartha Panda , Richard Wise , Srikanteswara Dakshina Murthy , Kamatchi Subramanian
发明人： Siddhartha Panda , Richard Wise , Srikanteswara Dakshina Murthy , Kamatchi Subramanian
IPC分类号： H01L21/461
CPC分类号： H01L21/31116 , H01L21/3185
摘要： Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon and a non-carbon containing fluorine source such as sulfur hexafluoride (SF6). The plasma may also include oxygen (O2) and the fluorohydrocarbons may include at least one of: trifluoromethane (CHF3), difluoromethane (CH2F2), and methyl fluoride (CH3F). In an alternative embodiment, the plasma includes one of hydrogen (H2) and nitrogen trifluoride (NF3) and one of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8). The methods are preferably carried out using a low bias voltage, e.g.
摘要翻译：公开了蚀刻氮化硅材料的方法，更具体地说，蚀刻对二氧化硅或硅化物有选择性的氮化物。所述方法包括将其上具有氮化硅的衬底暴露于包括至少一种氟代烃和不含碳的氟源如六氟化硫（SF 6 N 6）的等离子体。等离子体还可以包括氧（O 2 H 2），并且氟代烃可以包括以下中的至少一种：三氟甲烷（CHF 3 N 3），二氟甲烷（CH 2 N 2） > F 2）和氟化氟（CH 3 N 3 F）。在替代实施方案中，等离子体包括氢（H 2 H 2）和三氟化氮（NF 3 N）之一和四氟甲烷（CF 3 SO 3））和八氟环丁烷（C 4 H 8 F 8）。该方法优选使用低偏置电压进行，例如， <100 V.

7. 发明申请

US20060227321A1 NON-DESTRUCTIVE IN-SITU ELEMENTAL PROFILING 失效
标题翻译：非破坏性现场元素分析
公开(公告)号：US20060227321A1
公开(公告)日：2006-10-12
申请号：US10907591
申请日：2005-04-07
申请人： Siddhartha Panda , Michael Sievers , Richard Wise
发明人： Siddhartha Panda , Michael Sievers , Richard Wise
IPC分类号： G01J3/40
CPC分类号： G01N23/2273
摘要： A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.
摘要翻译：公开了一组层中的层的非破坏性原位元素分析方法和系统。在一个实施例中，多个光电子的第一次发射是从该层进行元素分析。基于发射确定层的元素分布。在另一个实施例中，也从该层接收多个光电子的第二次发射，并且通过比较所得到的信号来确定元素分布。然后可以“即时”控制改变层的方法以获得所需的材料组成。由于该方法可以原位使用并且是非破坏性的，所以可以减少周转时间并降低晶片消耗。本发明还记录了所有加工晶片的组成，因此，去除了常规统计抽样问题。

8. 发明申请

US20050112900A1 Method of processing wafers with resonant heating 失效
标题翻译：用共振加热处理晶片的方法
公开(公告)号：US20050112900A1
公开(公告)日：2005-05-26
申请号：US10721657
申请日：2003-11-25
申请人： Siddhartha Panda , Richard Wise
发明人： Siddhartha Panda , Richard Wise
IPC分类号： H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/461
CPC分类号： H01J37/32339 , H01L21/3065 , H01L21/32136
摘要： A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.
摘要翻译：使用谐振红外能量蚀刻晶片的方法和用于在等离子体蚀刻处理期间控制不均匀性的滤光器。滤波器包括可反映由等离子体蚀刻工艺引起的空间蚀刻失真的可变透射区域的预定阵列或堆叠布置。通过空间衰减到达晶片的IR能量的水平，滤波器改善了蚀刻工艺中的均匀性。滤波器可以被设计为补偿由于宏载荷，等离子体室中的不对称泵浦和磁场冲击造成的边缘快速蚀刻。

9. 发明授权

US07776695B2 Semiconductor device structure having low and high performance devices of same conductive type on same substrate 失效
标题翻译：具有相同基板上相同导电类型的低和高性能器件的半导体器件结构
公开(公告)号：US07776695B2
公开(公告)日：2010-08-17
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

10. 发明申请

US20080078743A1 ELEVATED TEMPERATURE CHEMICAL OXIDE REMOVAL MODULE AND PROCESS 审中-公开
标题翻译：高温化学氧化物去除模块和工艺
公开(公告)号：US20080078743A1
公开(公告)日：2008-04-03
申请号：US11536388
申请日：2006-09-28
申请人： Andres F. Munoz , Siddhartha Panda , Michael R. Sievers , Richard Wise
发明人： Andres F. Munoz , Siddhartha Panda , Michael R. Sievers , Richard Wise
IPC分类号： C03C25/68 , B44C1/22 , C23F1/00
CPC分类号： H01L21/67248 , H01L21/02057
摘要： A temperature-controlled substrate holder having a high temperature substrate chuck is mounted within a chemical treatment chamber. The temperature-controlled substrate holder secures a substrate and maintains the substrate at a temperature that ranges from about 10° C. up to about 150° C. during execution of a chemical oxide removal process.
摘要翻译：具有高温基板卡盘的温度控制的基板保持器安装在化学处理室内。温度控制的衬底保持器固定衬底并且在执行化学氧化物去除过程期间将衬底维持在约10℃至约150℃的温度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式