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1. 发明申请

US20070132473A1 Methods and apparatus for inline variability measurement of integrated circuit components 有权
标题翻译：集成电路元件在线可变性测量方法与装置
公开(公告)号：US20070132473A1
公开(公告)日：2007-06-14
申请号：US11297730
申请日：2005-12-08
申请人： Manjul Bhushan , Karen Gettings , Wilfried Haensch , Brian Ji , Mark Ketchen
发明人： Manjul Bhushan , Karen Gettings , Wilfried Haensch , Brian Ji , Mark Ketchen
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.
摘要翻译：提供了一种测量集成电路部件的可变性的方法。测量包括集成电路部件之间没有规定内部连接的多个集成电路部件的至少一个第一阵列配置的指定参数。还测量包括与集成电路部件之间具有规定的内部连接的第一阵列配置的名义上相同的多个集成电路部件的至少一个第二阵列配置的指定参数。基于所测量的至少一个第一阵列配置和至少一个第二阵列配置的指定参数，为集成电路组件确定变化系数。

2. 发明申请

US20050111567A1 ADAPTIVE DATA TRANSMITTER HAVING REWRITEABLE NON-VOLATILE STORAGE 失效
标题翻译：具有可逆非易失性存储的自适应数据传输器
公开(公告)号：US20050111567A1
公开(公告)日：2005-05-26
申请号：US10707199
申请日：2003-11-26
申请人： Louis Hsu , Brian Ji , William Washburn
发明人： Louis Hsu , Brian Ji , William Washburn
IPC分类号： H03H21/00 , H04L25/03 , H04L27/04
CPC分类号： H04L25/03343 , H03H21/0012
摘要： A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.
摘要翻译：提供了一种数据发送器和发送方法，其中自适应有限脉冲响应（FIR）驱动器具有应用具有可更新值的系数的多个抽头。 FIR驱动器在数据位的输入流和数据位的输出流之间具有传递函数，使得从FIR驱动器输出的每个数据位的幅度根据输入的多个数据位的值而被调整流，以及系数的值。数据发送器包括可重写的非易失性存储器，可操作以用表示在FIR驱动器的操作期间更新的系数的值的控制信息进行重写。

3. 发明申请

US20050071544A1 Segmented content addressable memory architecture for improved cycle time and reduced power consumption 有权
标题翻译：分段内容可寻址内存架构，可提高周期时间并降低功耗
公开(公告)号：US20050071544A1
公开(公告)日：2005-03-31
申请号：US10673801
申请日：2003-09-29
申请人： Louis Hsu , Brian Ji , Li-Kong Wang
发明人： Louis Hsu , Brian Ji , Li-Kong Wang
IPC分类号： G06F12/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.
摘要翻译：内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

4. 发明授权

US06636978B1 Rescheduling data input and output commands for bus synchronization by using digital latency shift detection 有权
标题翻译：通过使用数字等时移位检测重新安排数据输入和输出命令进行总线同步
公开(公告)号：US06636978B1
公开(公告)日：2003-10-21
申请号：US09441798
申请日：1999-11-17
申请人： Toshiaki Kirihata , L. Brian Ji , John Ross
发明人： Toshiaki Kirihata , L. Brian Ji , John Ross
IPC分类号： H04L700
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/222 , H03L7/0812
摘要： Digital latency shift communication problems from a driver chip to a receiver chip are overcome by scheduling a data output latency, a data input latency, a data output command, and/or a data output command, such that data outputted by the driver chip is received by the receiver chip at the correct time. A digital shift detection circuit detects the offset of the actual latencies from predetermined latencies. The offset of the latency is fed back to the scheduling circuit to override the predetermined latencies and/or command inputs that control the chip. The offset can be directly back-fed to the chip driver or chip receiver to compensate for digital shifts. Digital shift detection is achieved by measuring actual latencies with a manufacturing stand-alone tester, or with a built-in tester integral to the system. The digital shift detection predicts the conditions that create a digital shift by way of a mathematical model.
摘要翻译：通过调度数据输出延迟，数据输入延迟，数据输出命令和/或数据输出命令来克服从驱动器芯片到接收器芯片的数字等待时间移位通信问题，使得接收由驱动器芯片输出的数据由接收芯片在正确的时间。数字移位检测电路检测实际延迟与预定延迟的偏移。延迟的偏移被反馈到调度电路以覆盖控制芯片的预定延迟和/或命令输入。偏移可以直接回馈给芯片驱动器或芯片接收器，以补偿数字移位。数字移位检测通过使用制造独立测试仪测量实际延迟，或内置测试仪与系统集成来实现。数字移位检测预测了通过数学模型创建数字移位的条件。

5. 发明授权

US06185135B2 Robust wordline activation delay monitor using a plurality of sample wordlines 有权
标题翻译：使用多个样本字线的稳健的字线激活延迟监视器
公开(公告)号：US06185135B2
公开(公告)日：2001-02-06
申请号：US09225340
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C700
CPC分类号： G11C5/063
摘要： A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.
摘要翻译：公开了一种字线激活延迟监视电路，其中至少一个采样字线和采样字线冗余位于存储器的相同数据存储阵列区域内，并且采样字线选择器被耦合以激活采样字线或采样字线冗余处于非易失性输入状态。字线选择器电路可以包括行解码器电路或字线驱动器电路中的一个或两个，其具有与用于激活数据存储阵列区域内的字线的行解码器电路和字线驱动器电路基本相同的结构和位置。

6. 发明申请

US20060067440A1 High Speed Multi-Mode Receiver 有权
标题翻译：高速多模式接收机
公开(公告)号：US20060067440A1
公开(公告)日：2006-03-30
申请号：US10711713
申请日：2004-09-30
申请人： Louis Hsu , Brian Ji , James Mason , Karl Selander , Michael Sorna , Steven Zier
发明人： Louis Hsu , Brian Ji , James Mason , Karl Selander , Michael Sorna , Steven Zier
IPC分类号： H03K5/01 , H04B1/10 , H04L25/08
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译：提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

7. 发明授权

US6115310A Wordline activation delay monitor using sample wordline located in data-storing array 有权
标题翻译：字线激活延迟监视器使用位于数据存储阵列中的示例字线
公开(公告)号：US6115310A
公开(公告)日：2000-09-05
申请号：US225343
申请日：1999-01-05
申请人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
发明人： Dmitry G. Netis , L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C8/08 , G11C8/14 , G11C8/18 , G11C11/408 , G11C11/4091 , G11C7/02
CPC分类号： G11C8/18 , G11C11/408 , G11C11/4091 , G11C8/14
摘要： A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
摘要翻译：本文公开了一种字线激活延迟监视器电路，其包括位于存储器的数据存储阵列内的采样字线，其中采样字线由存储器内具有基本相同结构或位置的电路选择或激活，该电路选择或激活数据存储阵列的字线。公开了一种电路，其通过激活位于第二子阵列组的数据存储阵列内的采样字线来确定存储器内的第一子阵列组的字线激活延迟。还公开了相应的方法。

8. 发明授权

US6038634A Intra-unit block addressing system for memory 失效
标题翻译：内存单元块寻址系统
公开(公告)号：US6038634A
公开(公告)日：2000-03-14
申请号：US17017
申请日：1998-02-02
申请人： L. Brian Ji , Toshiaki Kirihata
发明人： L. Brian Ji , Toshiaki Kirihata
IPC分类号： G11C11/407 , G11C8/10 , G11C11/401 , G11C11/408 , G11C11/409 , G06F12/06
CPC分类号： G11C8/10
摘要： A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.
摘要翻译：本文公开了一种用于稳定与双存储器单元的第一和第二存储单元内的块访问相关的电流耗散，电压降和加热效应的系统。该系统包括位于第一和第二存储单元之间的行选择单元，其根据从双存储器单元的外端传输到所选行位置的第一和第二选择信号访问第一和第二存储单元的存储位置。与外部相对应的距离的块以不同的方式编号，使得第一和第二选择信号到编号的块的信号行程的长度之和保持相对恒定，而不管选择用于访问的块号。

9. 发明申请

US20070025144A1 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US20070025144A1
公开(公告)日：2007-02-01
申请号：US11193878
申请日：2005-07-29
申请人： Louis Hsu , Brian Ji , Chung Lam
发明人： Louis Hsu , Brian Ji , Chung Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

10. 发明申请

US20070002608A1 Non-volatile content addressable memory using phase-change-material memory elements 有权
标题翻译：使用相变材料存储元件的非易失性内容可寻址存储器
公开(公告)号：US20070002608A1
公开(公告)日：2007-01-04
申请号：US11172473
申请日：2005-06-30
申请人： Louis Hsu , Brian Ji , Chung Lam , Hon-Sum Wong
发明人： Louis Hsu , Brian Ji , Chung Lam , Hon-Sum Wong
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.
摘要翻译：非易失性内容可寻址存储单元包括：第一相变材料元件，所述第一相变材料元件具有连接到匹配线的一端; 第一晶体管，第一晶体管具有连接到字线的栅极，连接到真位读 - 写搜索线的源极和连接到第一相变材料元件的另一端的漏极; 第二相变材料元件，所述第二相变材料元件具有连接到所述匹配线的一端; 以及第二晶体管，所述第二晶体管具有连接到所述字线的栅极，连接到互补位读写搜索线的源极和连接到所述第二相变材料元件的另一端的漏极。

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