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1. 发明授权

US08629535B2 Mask for forming integrated circuit 有权
标题翻译：用于形成集成电路的掩模
公开(公告)号：US08629535B2
公开(公告)日：2014-01-14
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L23/58
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

2. 发明授权

US07709373B1 System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权
标题翻译：用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化
公开(公告)号：US07709373B1
公开(公告)日：2010-05-04
申请号：US11553220
申请日：2006-10-26
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A Phan
IPC分类号： H01L21/4763
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译：提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。电介质蚀刻将图案从转印层转移到电介质层中。然后，金属填充过程用金属填充介电层的双镶嵌开口。

3. 发明授权

US07432558B1 Formation of semiconductor devices to achieve <100> channel orientation 有权
标题翻译：形成半导体器件实现<100>通道方向
公开(公告)号：US07432558B1
公开(公告)日：2008-10-07
申请号：US10863392
申请日：2004-06-09
申请人： Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Bin Yu
发明人： Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Bin Yu
IPC分类号： H01L29/72
CPC分类号： H01L29/045 , H01L29/66795 , H01L29/785
摘要： A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.
摘要翻译：半导体器件可以包括衬底和形成在衬底上的绝缘层。可以在绝缘层上形成翅片。翅片可以包括侧表面和顶表面，并且侧表面可以具有<100>取向。第一栅极可以形成在靠近鳍片的侧表面的绝缘层上。

4. 发明授权

US07381278B1 Using supercritical fluids to clean lenses and monitor defects 有权
标题翻译：使用超临界流体清洁镜头并监测缺陷
公开(公告)号：US07381278B1
公开(公告)日：2008-06-03
申请号：US11555564
申请日：2006-11-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A Phan , Srikanteswara Dakshina-Murthy
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A Phan , Srikanteswara Dakshina-Murthy
IPC分类号： G03B27/42
CPC分类号： G03F7/2041 , G03F7/70341 , G03F7/70925
摘要： Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.
摘要翻译：公开了浸没式光刻方法，包括通过透镜和浸没液体照射第一光致抗蚀剂，浸没液体在第一装置中与透镜和第一光致抗蚀剂接触; 在第二装置中使透镜与超临界流体接触; 以及通过所述透镜和浸没液体照射第二光致抗蚀剂，所述浸没液体与所述透镜和所述第二光致抗蚀剂接触。

5. 发明授权

US07196372B1 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US07196372B1
公开(公告)日：2007-03-27
申请号：US10614177
申请日：2003-07-08
申请人： Bin Yu , Ming-Ren Lin , Srikanteswara Dakshina-Murthy , Zoran Krivokapic
发明人： Bin Yu , Ming-Ren Lin , Srikanteswara Dakshina-Murthy , Zoran Krivokapic
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11568 , H01L29/785
摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.
摘要翻译：非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。氧化层形成在翅片上并用作存储器件的隧道氧化物。间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。间隔件用作非易失性存储器件的浮栅电极。

6. 发明授权

US07156925B1 Using supercritical fluids to clean lenses and monitor defects 有权
标题翻译：使用超临界流体清洁镜头并监测缺陷
公开(公告)号：US07156925B1
公开(公告)日：2007-01-02
申请号：US10978844
申请日：2004-11-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan , Srikanteswara Dakshina-Murthy
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan , Srikanteswara Dakshina-Murthy
IPC分类号： G03B27/42
CPC分类号： G03F7/2041 , G03F7/70341 , G03F7/70925
摘要： Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.
摘要翻译：公开了浸没式光刻方法，包括通过透镜和浸没液体照射第一光致抗蚀剂，浸没液体在第一装置中与透镜和第一光致抗蚀剂接触; 在第二装置中使透镜与超临界流体接触; 以及通过所述透镜和浸没液体照射第二光致抗蚀剂，所述浸没液体与所述透镜和所述第二光致抗蚀剂接触。

7. 发明授权

US07122455B1 Patterning with rigid organic under-layer 有权
标题翻译：图案与刚性有机底层
公开(公告)号：US07122455B1
公开(公告)日：2006-10-17
申请号：US10790567
申请日：2004-03-01
申请人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
发明人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , Y10S438/942 , Y10S438/947
摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
摘要翻译：为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

8. 发明授权

US07065427B1 Optical monitoring and control of two layers of liquid immersion media 失效
标题翻译：两层液浸介质的光学监测与控制
公开(公告)号：US07065427B1
公开(公告)日：2006-06-20
申请号：US10979367
申请日：2004-11-01
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
IPC分类号： G06F19/00 , G02B7/00 , H01L21/00
CPC分类号： G03F7/7085 , G03F7/70341 , G03F7/70591
摘要： A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.
摘要翻译：用于光刻工艺的多层浸渍介质监测系统监测半导体制造工艺的浸渍介质的特性。多层浸渍介质至少包括第一密度（或粘度）的第一液体和较低密度（或粘度）的第二液体，它们都分散在最终的光学部件和半导体层之间。提供更高密度的层以在光刻过程中减少浸没介质中的湍流。散射测量系统监测多层浸没介质的光学特性，以实现光刻工艺的控制。

9. 发明申请

US20060121711A1 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效
标题翻译：用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法
公开(公告)号：US20060121711A1
公开(公告)日：2006-06-08
申请号：US11002586
申请日：2004-12-03
申请人： Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
发明人： Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译：在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定间隔件，同时采用紧密对准规格。

10. 发明授权

US06960804B1 Semiconductor device having a gate structure surrounding a fin 有权
标题翻译：具有围绕鳍片的栅极结构的半导体器件
公开(公告)号：US06960804B1
公开(公告)日：2005-11-01
申请号：US10633034
申请日：2003-10-10
申请人： Chih-Yuh Yang , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Bin Yu
发明人： Chih-Yuh Yang , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Bin Yu
IPC分类号： H01L21/027 , H01L21/336 , H01L29/786 , H01L29/788
CPC分类号： H01L29/785 , H01L21/0276 , H01L29/42392 , H01L29/66795
摘要： A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.
摘要翻译：双半导体器件包括衬底，绝缘层，鳍和栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。翅片具有多个侧表面，顶表面和底表面。栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

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