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1. 发明授权

US5097138A Electron beam lithography system and method 失效
标题翻译：电子束光刻系统及方法
公开(公告)号：US5097138A
公开(公告)日：1992-03-17
申请号：US563441
申请日：1990-08-07
申请人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
发明人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01L21/027 , H01J37/317
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/0453 , H01J2237/31769 , H01J2237/31776 , Y10S430/143
摘要： A system and method are provided for compensating for proximity effects between selected adjacent portions of pattern elements on an integrated circuit wafer where it is determined by simulation that undesirable resist patterns will result. The subject lithography system includes projecting an electron beam onto the wafer through an aperture plate of pattern elements to obtain the desired beam pattern. An aperture mask includes a plurality of first portions corresponding to first wafer circuit element portions spaced for avoiding proximity effects on the wafer and a plurality of second portions corresponding to second element portions spaced for obtaining proximity effects between elements on the wafer. The plurality of second portions are sized to have an increased adjacent spacing relative to a resultant adjacent spacing of the corresponding second element portions whereby the resultant adjacent spacing of the second element portions on the wafer is selectively reduced by the proximity effects. Alternatively, or in addition, a wire mesh is provided at the second portions of the aperture plate to reduce the beam intensity for corresponding reduction of the proximity effects.
摘要翻译：提供了一种用于补偿集成电路晶片上的图案元件的选定相邻部分之间的接近效应的系统和方法，其中通过模拟确定将导致不期望的抗蚀剂图案。目标光刻系统包括通过图案元件的孔板将电子束投影到晶片上，以获得期望的光束图案。孔径掩模包括对应于间隔开的第一晶片电路元件部分的多个第一部分，以避免对晶片的接近效应，以及对应于间隔开的第二元件部分的多个第二部分，以获得晶片上元件之间的接近效应。多个第二部分的大小相对于相应的第二元件部分的相邻相邻间隔具有增加的相邻间隔，由此通过邻近效应选择性地减小晶片上的第二元件部分的相邻间隔。或者，或另外，在孔板的第二部分处设置金属丝网以减小光束强度，以便相应地减小邻近效应。

2. 发明授权

US5424173A Electron beam lithography system and method 失效
公开(公告)号：US5424173A
公开(公告)日：1995-06-13
申请号：US158820
申请日：1993-11-26
申请人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
发明人： Hiroaki Wakabayashi , Osamu Suga , Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01L21/027 , H01J37/317 , G03F7/20
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/0453 , H01J2237/31769 , H01J2237/31776 , Y10S430/143
摘要： A system and method are provided for compensating for proximity effects between selected adjacent portions of pattern elements on an integrated circuit wafer where it is determined by simulation that undesirable resist patterns will result. The subject lithography system includes projecting an electron beam onto the wafer through an aperture plate of pattern elements to obtain the desired beam pattern. An aperture mask includes a plurality of first portions corresponding to first wafer circuit element portions spaced for avoiding proximity effects on the wafer and a plurality of second portions corresponding to second element portions spaced for obtaining proximity effects between elements on the wafer. The plurality of second portions are sized to have an increased adjacent spacing relative to a resultant adjacent spacing of the corresponding second element portions whereby the resultant adjacent spacing of the second element portions on the wafer is selectively reduced by the proximity effects. Alternatively, or in addition, a wire mesh is provided at the second portions of the aperture plate to reduce the beam intensity for corresponding reduction of the proximity effects.

3. 发明授权

US5334845A Charged beam exposure method and apparatus as well as aperture stop and production method thereof 失效
标题翻译：充电束曝光方法和装置以及孔径光阑及其制造方法
公开(公告)号：US5334845A
公开(公告)日：1994-08-02
申请号：US613746
申请日：1990-11-26
申请人： Hiroaki Wakabayashi , Yoshinori Nakayama , Fumio Murai , Shinji Okazaki
发明人： Hiroaki Wakabayashi , Yoshinori Nakayama , Fumio Murai , Shinji Okazaki
IPC分类号： H01J37/317 , H01L21/027
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/31776 , H01J2237/31788
摘要： In an electron beam exposure method for production very high-integration semiconductor devices and its related apparatus in a conventional method, the exposure is divided into fine divisions and carried out by performing a number of shots. However, by utilizing an aperture stop produced by working a single crystalline silicon thin film finely, exposure of a predetermined range is done by one shot. According to the invention, the exposure can be accomplished by the number of shots which is smaller by about two orders than that of the conventional technique and the throughput can be improved remarkably. Since the shot number does not substantially differ depending on whether patterns are complicated or not, individual steps can be processed within substantially identical time.
摘要翻译： PCT No.PCT / JP90 / 00388 Sec。 371日期1990年11月26日 102（e）1990年11月26日PCT PCT 1990年3月23日PCT公布。公开号WO90 / 11619 日期为1990年10月4日。在以往的方法中，为了制造非常高集成度的半导体装置及其相关装置的电子束曝光方法，将曝光分割为细分，并进行多次拍摄。然而，通过利用通过微细加工单晶硅薄膜产生的孔径光阑，通过一次曝光实现预定范围。根据本发明，曝光可以通过比常规技术小两个点的拍摄次数来实现，并且可以显着地提高吞吐量。由于根据图案是否复杂，拍摄次数基本上不同，所以可以在大致相同的时间内处理各个步骤。

4. 发明授权

US08064681B2 Method and apparatus for inspecting reticle 有权
标题翻译：检查掩模版的方法和装置
公开(公告)号：US08064681B2
公开(公告)日：2011-11-22
申请号：US12292660
申请日：2008-11-24
申请人： Nobuhiro Okai , Shinji Okazaki , Yasunari Sohda , Yoshinori Nakayama
发明人： Nobuhiro Okai , Shinji Okazaki , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： G06K9/00
CPC分类号： G06K9/00 , G06K2209/19 , G06T7/0004
摘要： The present invention provides a reticle inspection technology that enables a relative position between patterns to be evaluated for a pattern that may become a defect at the time of exposure to a sample, such as a wafer, in the double patterning technology on the same layer. An apparatus for inspecting a reticle for inspecting two reticles that are used in order to form patterns in the same layer on a substrate using the double patterning technology has: a coordinate information input unit for inputting coordinate information of a pattern of a measuring object; an image input unit for acquiring images of patterns of the two reticles based on the obtained coordinate information; an image overlay unit for overlaying the images of the two reticles at the same coordinates; a relative position calculation unit for finding the relative position between the patterns on the two reticles; an evaluation unit for assigning an index of the overlaying accuracy based on the relative position and evaluates whether the two reticles need repair; and an evaluation result output unit for outputting an evaluation result.
摘要翻译：本发明提供了一种掩模版检查技术，其能够在同一层上的双重图案化技术中，使图案之间的相对位置能够在暴露于样品（例如晶片）时成为缺陷的图案被评估。用于检查用于检查用于使用双重图案形成技术在基板上形成图案的图案的两个掩模版的掩模版的装置具有：用于输入测量对象的图案的坐标信息的坐标信息输入单元; 图像输入单元，用于基于所获得的坐标信息获取两个标线图案的图像; 用于在相同坐标处叠加两个光罩的图像的图像叠加单元; 相对位置计算单元，用于找到两个标线之间的图案之间的相对位置; 评估单元，用于基于所述相对位置分配所述重叠精度的指标，并评估所述两个标线是否需要修理; 以及评价结果输出单元，用于输出评估结果。

5. 发明授权

US5283440A Electron beam writing system used in a cell projection method 失效
标题翻译：电子束写入系统用于单元投影法
公开(公告)号：US5283440A
公开(公告)日：1994-02-01
申请号：US770527
申请日：1991-10-03
申请人： Yasunari Sohda , Hideo Todokoro , Norio Saitou , Haruo Yoda , Hiroyuki Itoh , Hiroyuki Shinada , Yoshinori Nakayama , Shinji Okazaki
发明人： Yasunari Sohda , Hideo Todokoro , Norio Saitou , Haruo Yoda , Hiroyuki Itoh , Hiroyuki Shinada , Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01J37/317 , H01J37/30
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/049 , H01J2237/1532 , H01J2237/30455 , H01J2237/31776
摘要： An electron beam writing system is used in variable shaping and cell projection methods to produce LSI and reticles. In the cell projection method, the beam is deflected to define a writing position. In the time it takes to define the writing position, an operation of forming the beam is concluded, which operation includes the deflection of the beam to select a cell graphic, re-deflection for correcting the origin position of the written graphic, astigmatism correction of the written graphic, and focus correction for reducing the Coulomb effect. An electrostatic deflector is used as the deflector for the cell graphic selection. The arrangement of graphics includes a square aperture centrally located with a group of cell projection apertures positioned adjacent two sides of the square aperture.
摘要翻译：电子束写入系统用于可变整形和电池投影方法以产生LSI和光罩。在单元投影方法中，光束被偏转以限定写入位置。在定义写入位置的时候，结束了形成光束的操作，其操作包括光束的偏转以选择单元图形，用于校正写入图形的原点位置的重新偏转，散光校正书面图形和焦点校正，以减少库仑效应。静电偏转器用作细胞图形选择的偏转器。图形的布置包括中心定位的方孔，其中一组单元突出孔定位成邻近正方形孔的两侧。

6. 发明授权

US07943903B2 Defect inspection method and its system 有权
标题翻译：缺陷检查方法及其系统
公开(公告)号：US07943903B2
公开(公告)日：2011-05-17
申请号：US12320574
申请日：2009-01-29
申请人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
发明人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： H01J37/153 , G01N23/00
CPC分类号： H01L22/12 , G06T7/0006 , G06T7/001 , G06T2207/10056 , G06T2207/30148 , H01L2924/0002 , H01L2924/00
摘要： A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
摘要翻译：一种能够容易地管理半导体集成图案的致命缺陷的方法，该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据，以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据分别。该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷，同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上，并将这些缺陷存储为热点信息。此外，该方法还能够将设计意图数据与热点信息组合，以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点，并显着缩短缺陷检查时间。

7. 发明申请

US20090136116A1 Method and apparatus for inspecting reticle 有权
标题翻译：检查掩模版的方法和装置
公开(公告)号：US20090136116A1
公开(公告)日：2009-05-28
申请号：US12292660
申请日：2008-11-24
申请人： Nobuhiro Okai , Shinji Okazaki , Yasunari Sohda , Yoshinori Nakayama
发明人： Nobuhiro Okai , Shinji Okazaki , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： G06K9/00
CPC分类号： G06K9/00 , G06K2209/19 , G06T7/0004
摘要： The present invention provides a reticle inspection technology that enables a relative position between patterns to be evaluated for a pattern that may become a defect at the time of exposure to a sample, such as a wafer, in the double patterning technology on the same layer. An apparatus for inspecting a reticle for inspecting two reticles that are used in order to form patterns in the same layer on a substrate using the double patterning technology has: a coordinate information input unit for inputting coordinate information of a pattern of a measuring object; an image input unit for acquiring images of patterns of the two reticles based on the obtained coordinate information; an image overlay unit for overlaying the images of the two reticles at the same coordinates; a relative position calculation unit for finding the relative position between the patterns on the two reticles; an evaluation unit for assigning an index of the overlaying accuracy based on the relative position and evaluates whether the two reticles need repair; and an evaluation result output unit for outputting an evaluation result.
摘要翻译：本发明提供了一种掩模版检查技术，其能够在同一层上的双重图案化技术中，使图案之间的相对位置能够在暴露于样品（例如晶片）时成为缺陷的图案被评估。用于检查用于检查用于使用双重图案形成技术在基板上形成图案的图案的两个掩模版的掩模版的装置具有：用于输入测量对象的图案的坐标信息的坐标信息输入单元; 图像输入单元，用于基于所获得的坐标信息获取两个标线图案的图像; 用于在相同坐标处叠加两个光罩的图像的图像叠加单元; 相对位置计算单元，用于找到两个标线之间的图案之间的相对位置; 评估单元，用于基于所述相对位置分配所述重叠精度的指标，并评估所述两个标线是否需要修理; 以及评价结果输出单元，用于输出评估结果。

8. 发明授权

US5334282A Electron beam lithography system and method 失效
标题翻译：电子束光刻系统及方法
公开(公告)号：US5334282A
公开(公告)日：1994-08-02
申请号：US765252
申请日：1991-09-25
申请人： Yoshinori Nakayama , Shinji Okazaki
发明人： Yoshinori Nakayama , Shinji Okazaki
IPC分类号： H01L21/027 , B23K15/00 , G03F7/20 , H01J37/317 , A61K27/02
CPC分类号： B82Y10/00 , B23K15/0013 , B82Y40/00 , G03F7/2061 , H01J37/3174 , H01J2237/30472 , H01J2237/31767 , H01J2237/31769 , H01J2237/31776 , Y10S438/946 , Y10S438/949
摘要： An electron beam lithography system and method which provide an in-plane current density distribution of an electron beam focussed onto a specimen so as to prevent a proximity effect and space charge effect.
摘要翻译：提供电子束光刻系统和方法，其提供聚焦在样本上的电子束的面内电流密度分布，以防止接近效应和空间电荷效应。

9. 发明授权

US4740693A Electron beam pattern line width measurement system 失效
标题翻译：电子束图案线宽测量系统
公开(公告)号：US4740693A
公开(公告)日：1988-04-26
申请号：US807681
申请日：1985-12-11
申请人： Yoshinori Nakayama , Shinji Okazaki , Hidehito Obayashi , Mikio Ichihashi
发明人： Yoshinori Nakayama , Shinji Okazaki , Hidehito Obayashi , Mikio Ichihashi
IPC分类号： G01S13/74 , G01B7/02 , G01B15/00 , H01J37/28 , G01B7/14
CPC分类号： H01J37/28 , G01B15/00 , G01B7/02
摘要： Disclosed is an electron beam pattern line width measurement system wherein an electron beam is converged to a fine spot, the electron beam is scanned on a sample formed with a pattern to-be-measured, secondary electrons generated from a surface of the sample by the projection of the electron beam are detected, and the detected signal is processed to determine a line width of the pattern to-be-measured, comprising a secondary electron detector which detects a signal corresponding to an amount of all secondary electrons generated by the scanning, and a secondary electron energy analyzer which selectively detects a signal corresponding to an amount of secondary electrons of specified energy. With the electron beam pattern line width measurement system, it becomes possible to precisely detect a pattern boundary region defined by different sorts of materials in a stepped structure of a small level difference not having been measurable with a prior-art electron beam pattern line width measurement system.
摘要翻译：公开了一种电子束图案线宽度测量系统，其中电子束会聚到细微点，电子束在形成有要测量图案的样品上扫描，从样品表面产生的二次电子被检测电子束的投影，并且处理检测信号以确定要测量的图案的线宽，包括二次电子检测器，其检测对应于由扫描产生的所有二次电子的量的信号，以及二次电子能量分析器，其选择性地检测与特定能量的二次电子量对应的信号。利用电子束图案线宽度测量系统，可以精确地检测由现有技术的电子束图案线宽度测量不能测量的小电平差的阶梯式结构中由不同种类的材料限定的图案边界区域系统。

10. 发明申请

US20090206252A1 Defect inspection method and its system 有权
标题翻译：缺陷检查方法及其系统
公开(公告)号：US20090206252A1
公开(公告)日：2009-08-20
申请号：US12320574
申请日：2009-01-29
申请人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
发明人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： G01N23/00
CPC分类号： H01L22/12 , G06T7/0006 , G06T7/001 , G06T2207/10056 , G06T2207/30148 , H01L2924/0002 , H01L2924/00
摘要： A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
摘要翻译：一种能够容易地管理半导体集成图案的致命缺陷的方法，该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据，以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据分别。该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷，同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上，并将这些缺陷存储为热点信息。此外，该方法还能够将设计意图数据与热点信息组合，以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点，并显着缩短缺陷检查时间。

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