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    • 1. 发明申请
    • Defect inspection method and its system
    • 缺陷检查方法及其系统
    • US20090206252A1
    • 2009-08-20
    • US12320574
    • 2009-01-29
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • G01N23/00
    • H01L22/12G06T7/0006G06T7/001G06T2207/10056G06T2207/30148H01L2924/0002H01L2924/00
    • A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
    • 一种能够容易地管理半导体集成图案的致命缺陷的方法,该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据,以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据 分别。 该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷,同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上,并将这些缺陷存储为热点信息。 此外,该方法还能够将设计意图数据与热点信息组合,以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点,并显着缩短缺陷检查时间。
    • 2. 发明授权
    • Defect inspection method and its system
    • 缺陷检查方法及其系统
    • US07943903B2
    • 2011-05-17
    • US12320574
    • 2009-01-29
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • Shinji OkazakiShoji HottaYasunari SohdaYoshinori Nakayama
    • H01J37/153G01N23/00
    • H01L22/12G06T7/0006G06T7/001G06T2207/10056G06T2207/30148H01L2924/0002H01L2924/00
    • A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
    • 一种能够容易地管理半导体集成图案的致命缺陷的方法,该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据,以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据 分别。 该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷,同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上,并将这些缺陷存储为热点信息。 此外,该方法还能够将设计意图数据与热点信息组合,以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点,并显着缩短缺陷检查时间。
    • 5. 发明申请
    • Method and apparatus for inspecting reticle
    • 检查掩模版的方法和装置
    • US20090136116A1
    • 2009-05-28
    • US12292660
    • 2008-11-24
    • Nobuhiro OkaiShinji OkazakiYasunari SohdaYoshinori Nakayama
    • Nobuhiro OkaiShinji OkazakiYasunari SohdaYoshinori Nakayama
    • G06K9/00
    • G06K9/00G06K2209/19G06T7/0004
    • The present invention provides a reticle inspection technology that enables a relative position between patterns to be evaluated for a pattern that may become a defect at the time of exposure to a sample, such as a wafer, in the double patterning technology on the same layer. An apparatus for inspecting a reticle for inspecting two reticles that are used in order to form patterns in the same layer on a substrate using the double patterning technology has: a coordinate information input unit for inputting coordinate information of a pattern of a measuring object; an image input unit for acquiring images of patterns of the two reticles based on the obtained coordinate information; an image overlay unit for overlaying the images of the two reticles at the same coordinates; a relative position calculation unit for finding the relative position between the patterns on the two reticles; an evaluation unit for assigning an index of the overlaying accuracy based on the relative position and evaluates whether the two reticles need repair; and an evaluation result output unit for outputting an evaluation result.
    • 本发明提供了一种掩模版检查技术,其能够在同一层上的双重图案化技术中,使图案之间的相对位置能够在暴露于样品(例如晶片)时成为缺陷的图案被评估。 用于检查用于检查用于使用双重图案形成技术在基板上形成图案的图案的两个掩模版的掩模版的装置具有:用于输入测量对象的图案的坐标信息的坐标信息输入单元; 图像输入单元,用于基于所获得的坐标信息获取两个标线图案的图像; 用于在相同坐标处叠加两个光罩的图像的图像叠加单元; 相对位置计算单元,用于找到两个标线之间的图案之间的相对位置; 评估单元,用于基于所述相对位置分配所述重叠精度的指标,并评估所述两个标线是否需要修理; 以及评价结果输出单元,用于输出评估结果。
    • 6. 发明授权
    • Method and apparatus for inspecting reticle
    • 检查掩模版的方法和装置
    • US08064681B2
    • 2011-11-22
    • US12292660
    • 2008-11-24
    • Nobuhiro OkaiShinji OkazakiYasunari SohdaYoshinori Nakayama
    • Nobuhiro OkaiShinji OkazakiYasunari SohdaYoshinori Nakayama
    • G06K9/00
    • G06K9/00G06K2209/19G06T7/0004
    • The present invention provides a reticle inspection technology that enables a relative position between patterns to be evaluated for a pattern that may become a defect at the time of exposure to a sample, such as a wafer, in the double patterning technology on the same layer. An apparatus for inspecting a reticle for inspecting two reticles that are used in order to form patterns in the same layer on a substrate using the double patterning technology has: a coordinate information input unit for inputting coordinate information of a pattern of a measuring object; an image input unit for acquiring images of patterns of the two reticles based on the obtained coordinate information; an image overlay unit for overlaying the images of the two reticles at the same coordinates; a relative position calculation unit for finding the relative position between the patterns on the two reticles; an evaluation unit for assigning an index of the overlaying accuracy based on the relative position and evaluates whether the two reticles need repair; and an evaluation result output unit for outputting an evaluation result.
    • 本发明提供了一种掩模版检查技术,其能够在同一层上的双重图案化技术中,使图案之间的相对位置能够在暴露于样品(例如晶片)时成为缺陷的图案被评估。 用于检查用于检查用于使用双重图案形成技术在基板上形成图案的图案的两个掩模版的掩模版的装置具有:用于输入测量对象的图案的坐标信息的坐标信息输入单元; 图像输入单元,用于基于所获得的坐标信息获取两个标线图案的图像; 用于在相同坐标处叠加两个光罩的图像的图像叠加单元; 相对位置计算单元,用于找到两个标线之间的图案之间的相对位置; 评估单元,用于基于所述相对位置分配所述重叠精度的指标,并评估所述两个标线是否需要修理; 以及评价结果输出单元,用于输出评估结果。