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1. 发明公开

US20230297338A1 Float Division by Constant Integer 审中-公开
公开(公告)号：US20230297338A1
公开(公告)日：2023-09-21
申请号：US18140571
申请日：2023-04-27
申请人： Imagination Technologies Limited
发明人： Jonas KALLEN , Sam ELLIOTT
IPC分类号： G06F7/556 , G06F7/72 , G06F7/487
CPC分类号： G06F7/556 , G06F7/4873 , G06F7/727
摘要： A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b > a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M - 1 modulo units of the logarithmic tree provide x[0: m]mod d for all m ∈ {1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of log2 M; and more than M - 2u of the subset of modulo units are arranged at the maximal delay of log2 M, where 2u is the power of 2 immediately smaller than M.

2. 发明授权

US11645042B2 Float division by constant integer 有权
公开(公告)号：US11645042B2
公开(公告)日：2023-05-09
申请号：US17547071
申请日：2021-12-09
申请人： Imagination Technologies Limited
发明人： Jonas Kallen , Sam Elliott
IPC分类号： G06F7/556 , G06F7/72 , G06F7/487
CPC分类号： G06F7/556 , G06F7/4873 , G06F7/727
摘要： A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log 2M┐; and more than M−2u of the subset of modulo units are arranged at the maximal delay of ┌log 2M┐, where 2u is the power of 2 immediately smaller than M.

3. 发明授权

US09753694B2 Division and root computation with fast result formatting 有权
公开(公告)号：US09753694B2
公开(公告)日：2017-09-05
申请号：US14692071
申请日：2015-04-21
申请人： QUALCOMM Incorporated
发明人： Kenneth Alan Dockser , Michael Thomas Dibrino , Pathik Sunil Lall
IPC分类号： G06F7/537 , G06F7/535 , G06F5/01 , G06F7/487
CPC分类号： G06F7/535 , G06F5/01 , G06F7/4873 , G06F7/5375 , G06F2205/003 , G06F2207/535
摘要： Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

4. 发明申请

US20170199723A1 CIRCUITRY AND METHOD FOR PERFORMING DIVISION 审中-公开
公开(公告)号：US20170199723A1
公开(公告)日：2017-07-13
申请号：US14994601
申请日：2016-01-13
申请人： ARM LIMITED
发明人： Javier Diaz BRUGUERA
IPC分类号： G06F7/491 , G06F7/487
CPC分类号： G06F7/487 , G06F7/4873 , G06F7/537 , G06F2207/5351
摘要： A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer power of 2 and greater than 1. Said division algorithm comprises a plurality of iterations, each of said plurality of iterations being performed by quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1] based on a remainder value of a previous iteration rem[i]; and remainder calculation circuitry to determine a remainder value of that iteration rem[i+1] based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i]. Result calculation circuitry derives said result value q based on each quotient value selected by said digit selection circuitry for each of said plurality of iterations. For at least some of said plurality of iterations, said quotient digit calculation circuitry speculatively determines a set of candidate values before a quotient value of said previous iteration is known and, in response to said quotient value of said previous iteration becoming known, determines said quotient value of that iteration q[i+1] based on one of said candidate values.

5. 发明授权

US08775494B2 System and method for testing whether a result is correctly rounded 有权
标题翻译：用于测试结果是否正确四舍五入的系统和方法
公开(公告)号：US08775494B2
公开(公告)日：2014-07-08
申请号：US13038193
申请日：2011-03-01
申请人： Alexandru Fit-Florea
发明人： Alexandru Fit-Florea
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/4873 , G06F7/49942 , G06F7/5525 , G06F2207/5355 , G06F2207/5356
摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.
摘要翻译：公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

6. 发明申请

US20140059096A1 DIVIDING DEVICE AND DIVIDING METHOD 审中-公开
标题翻译：分割装置和分割方法
公开(公告)号：US20140059096A1
公开(公告)日：2014-02-27
申请号：US13921238
申请日：2013-06-19
申请人： FUJITSU LIMITED
发明人： Kenichi Kitamura
IPC分类号： G06F5/01 , G06F7/485 , G06F7/487
CPC分类号： G06F5/012 , G06F7/485 , G06F7/487 , G06F7/4873 , G06F7/4917 , G06F7/49957
摘要： A dividing device includes: shifting circuits which left-shift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which calculates a quotient digit number expected value based on the first count value and the second count value; a dividing circuit which outputs a quotient and a remainder in sequence on a digit-by-digit basis based on the mantissa parts of the dividend and the divisor left-shifted by the shifting circuits; a subtracting circuit which subtracts an exponent part of the floating-point number being the divisor from an exponent part of the floating-point number being the dividend to output a resultant value; and a control circuit which outputs a mantissa part and an exponent part of a floating-point number being a quotient.
摘要翻译：分割装置包括：移位电路，其将所述被除数的尾数部分和除数乘以第一和第二计数值; 数字运算电路，其基于所述第一计数值和所述第二计数值计算商数位数预期值; 分频电路，基于乘数的尾数部分和由移位电路左移的除数，逐位地依次输出商和余数; 减法电路，从作为被除数的浮点数的指数部分中减去作为除数的浮点数的指数部分，输出结果值; 以及输出作为商的浮点数的尾数部分和指数部分的控制电路。

7. 发明授权

US08185723B2 Method and apparatus to extract integer and fractional components from floating-point data 有权
$Method and apparatus to extract integer and fractional components from floating-point data$
标题翻译：从浮点数据中提取整数和分数分量的方法和装置
公开(公告)号：US08185723B2
公开(公告)日：2012-05-22
申请号：US10483279
申请日：2001-07-13
申请人： Robert S. Norin , Olga Dryzhakova , Alexander Isaev , Andrey Naraikin
发明人： Robert S. Norin , Olga Dryzhakova , Alexander Isaev , Andrey Naraikin
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/72 , H03M7/24
摘要： A method is presented including decomposing a first value into many parts. Decomposing includes shifting (310) a rounded integer portion of the first value to generate a second value. Generating (320) a third value. Extracting (330) a plurality of significand bits from the second value to generate a fourth value. Extracting (340) a portion of bits from the fourth value to generate an integer component. Generating (350) a fifth value. Also the third value, the fifth value, and the integer component are either stored (360, 380) in a memory or transmitted to an arithmetic logical unit (ALU).
摘要翻译：提出了一种方法，包括将第一个值分解成许多部分。分解包括移位（310）第一值的圆整整数部分以生成第二值。生成（320）第三个值。从第二值提取（330）多个有效位以产生第四值。从第四个值提取（340）一部分位以产生整数分量。生成（350）第五个值。另外，第三值，第五值和整数分量在存储器中存储（360,380）或发送到算术逻辑单元（ALU）。

8. 发明授权

US07962543B2 Division with rectangular multiplier supporting multiple precisions and operand types 有权
标题翻译：具有矩形乘法器的分支，支持多种精度和操作数类型
公开(公告)号：US07962543B2
公开(公告)日：2011-06-14
申请号：US11756885
申请日：2007-06-01
申请人： Michael J. Schulte , Carl E. Lemonds, Jr. , Dimitri Tan
发明人： Michael J. Schulte , Carl E. Lemonds, Jr. , Dimitri Tan
IPC分类号： G06F7/535
CPC分类号： G06F7/4873 , G06F2207/5356
摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
摘要翻译：分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。每个算法计算一个或多个中间值以确定商。例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。基于这些中间值中的一个或多个的一部分来确定商。因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。

9. 发明申请

US20090216823A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING FLOATING POINT DIVIDE OPERATION RESULTS 有权
标题翻译：方法，系统和计算机程序产品用于验证浮点运算结果
公开(公告)号：US20090216823A1
公开(公告)日：2009-08-27
申请号：US12036397
申请日：2008-02-25
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/487 , G06F17/10
CPC分类号： G06F7/4873
摘要： A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.
摘要翻译：提供了用于验证浮点除法运算结果的方法，系统和计算机程序产品。该方法包括：接收分红和除数的浮点除法运算结果; 执行除数的最低有效位（LSB）的大小与余数的最高有效位（MSB）的大小的比较; 以及基于所述比较来确定所述结果是否正确。

10. 发明申请

US20090164543A1 APPARATUS AND METHOD TO COMPUTE RECIPROCAL APPROXIMATIONS 失效
标题翻译：用于计算近似近似的装置和方法
公开(公告)号：US20090164543A1
公开(公告)日：2009-06-25
申请号：US11963833
申请日：2007-12-23
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/483
CPC分类号： G06F7/4873
摘要： A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.
摘要翻译：提出了一种用于减少存储相对近似值所需的存储器的方法和装置，如IEEE电气和电子工程师协会（IEEE）标准如IEEE 754所规定。互逆函数的单调属性用于约束值组。有效的比特向量用于表示组中的信息，导致非常紧凑的表格表示比存储表中的所有倒数近似的四倍小。

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