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1. 发明授权

US06667212B1 Alignment system for planar charge trapping dielectric memory cell lithography 有权
标题翻译：平面电荷俘获介质存储单元光刻对准系统
公开(公告)号：US06667212B1
公开(公告)日：2003-12-23
申请号：US10394565
申请日：2003-03-21
申请人： Hidehiko Shiraiwa , Jean Yee-Mei Yang , Kouros Ghandehari
发明人： Hidehiko Shiraiwa , Jean Yee-Mei Yang , Kouros Ghandehari
IPC分类号： H01L218242
CPC分类号： H01L27/11568 , G03F7/70425 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/105 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a charge trapping dielectric memory cell array comprises exposing a first photoresist to a first illumination pattern from a first mask to pattern bit line regions in a core region of the wafer and to pattern alignment mark regions. The alignment mark regions may be in a scribe lane region of the wafer. An impurity is implanted into the wafer within the bit line regions and the alignment mark regions and an oxide is grown on the surface of the wafer in the scribe lane region to produce oxide protrusions within the alignment mark regions. A second photoresist is exposed to a second illumination pattern from a second mask to pattern word line regions within the core region of the wafer and utilizing surface height variations of the oxide protrusions to detect alignment between the second mask and the first mask.
摘要翻译：一种制造电荷俘获介质存储单元阵列的方法包括将第一光致抗蚀剂从第一掩模暴露于第一照明图案，以在晶片的芯区域中图案化位线区域，并且形成对准标记区域。对准标记区域可以在晶片的划线路区域中。在位线区域和对准标记区域内的晶片中注入杂质，在划线路区域的晶片表面生长氧化物，在对准标记区域内产生氧化物突起。第二光致抗蚀剂从第二掩模暴露于第二照明图案，以在晶片的芯区域内图案化字线区域，并且利用氧化物突起的表面高度变化来检测第二掩模和第一掩模之间的对准。

2. 发明授权

US06894342B1 Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control 有权
标题翻译：用于防止存储单元中的紫外线辐射损伤的结构和方法，并改善接触式CD控制
公开(公告)号：US06894342B1
公开(公告)日：2005-05-17
申请号：US10460278
申请日：2003-06-12
申请人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
发明人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
IPC分类号： H01L21/336 , H01L21/8246 , H01L23/532 , H01L23/552 , H01L29/788
CPC分类号： H01L27/11568 , H01L23/53295 , H01L23/552 , H01L27/112 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over at least one memory cell and over the substrate. The structure further comprises a first antireflective coating layer situated over the interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises a second antireflective coating layer situated directly over the first anti reflective coating layer. Either the first antireflective coating layer or second antireflective coating layer must be a silicon-rich layer. The first antireflective coating layer and the second antireflective coating may form a UV radiation blocking layer having a UV transparency less than approximately 1.0 percent, for example.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。至少一个存储单元可以是例如SONOS闪存单元。该结构还包括位于至少一个存储器单元上方和衬底上方的层间电介质层。该结构还包括位于层间电介质层上的第一抗反射涂层。根据该示例性实施例，该结构还包括直接位于第一抗反射涂层上的第二抗反射涂层。第一抗反射涂层或第二抗反射涂层必须是富硅层。第一抗反射涂层和第二抗反射涂层可以形成例如UV透明度小于约1.0％的UV辐射阻挡层。

3. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

4. 发明授权

US07538026B1 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US07538026B1
公开(公告)日：2009-05-26
申请号：US11098262
申请日：2005-04-04
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

5. 发明授权

US07070911B1 Structure and method for reducing standing waves in a photoresist 失效
标题翻译：用于降低光致抗蚀剂中的驻波的结构和方法
公开(公告)号：US07070911B1
公开(公告)日：2006-07-04
申请号：US10350472
申请日：2003-01-23
申请人： Dawn Hopper , Kouros Ghandehari , Minh Van Ngo
发明人： Dawn Hopper , Kouros Ghandehari , Minh Van Ngo
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , Y10S430/151
摘要： A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.
摘要翻译：提出了一种用于在制造半导体期间降低光致抗蚀剂中的驻波的结构和方法。本发明的实施例包括一种在制造半导体器件期间减少光致抗蚀剂中的驻波形成的方法，包括沉积具有高于材料的消光系数的第一抗反射涂层，以及沉积具有高于上述消光系数的第二抗反射涂层第一抗反射涂层，使得第一抗反射涂层和第二抗反射涂层在光刻工艺期间减少光致抗蚀剂中驻波的形成。

6. 发明授权

US06872609B1 Narrow bitline using Safier for mirrorbit 有权
标题翻译：使用Safier进行镜像位的窄位线
公开(公告)号：US06872609B1
公开(公告)日：2005-03-29
申请号：US10755430
申请日：2004-01-12
申请人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
发明人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
IPC分类号： H01L21/337 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。在形成过程中采用Safier材料以减小存储器中的埋置位线的尺寸，其适用于存储用于计算机等的数据。较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

7. 发明授权

US06642148B1 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist 失效
标题翻译： RELACS收缩方法应用于使用化学放大DUV型光致抗蚀剂的LDD或埋入式位线植入物的单面抗蚀剂掩模
公开(公告)号：US06642148B1
公开(公告)日：2003-11-04
申请号：US10126326
申请日：2002-04-19
申请人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
发明人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/0274 , H01L21/31144 , H01L21/743 , H01L27/112 , H01L27/11521 , H01L27/11568
摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.
摘要翻译：本发明一般涉及一种在半导体衬底内形成渐变结的方法。在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

8. 发明授权

US06403500B1 Cross-shaped resist dispensing system and method 有权
标题翻译：十字形抗蚀剂分配系统及方法
公开(公告)号：US06403500B1
公开(公告)日：2002-06-11
申请号：US09760241
申请日：2001-01-12
申请人： James Jiahua Yu , Kouros Ghandehari , Bhanwar Singh
发明人： James Jiahua Yu , Kouros Ghandehari , Bhanwar Singh
IPC分类号： H01L2131
CPC分类号： H01L21/6715 , G03F7/162
摘要： An exemplary method of depositing photoresist material on an integrated circuit wafer is described. This method can include providing a cross-shaped resist dispenser including a plurality of resist dispense nozzles; dispensing photoresist material through the plurality of resist dispense nozzles to an integrated circuit wafer; and rotating at least one of the cross-shaped resist dispenser and the integrated circuit wafer.
摘要翻译：描述了在集成电路晶片上沉积光致抗蚀剂材料的示例性方法。该方法可以包括提供包括多个抗蚀剂分配喷嘴的十字形抗蚀剂分配器; 将光致抗蚀剂材料通过所述多个抗蚀剂分配喷嘴分配到集成电路晶片; 以及旋转十字形抗蚀剂分配器和集成电路晶片中的至少一个。

9. 发明授权

US08309457B2 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US08309457B2
公开(公告)日：2012-11-13
申请号：US13283076
申请日：2011-10-27
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

10. 发明授权

US07572727B1 Semiconductor formation method that utilizes multiple etch stop layers 有权
标题翻译：利用多个蚀刻停止层的半导体形成方法
公开(公告)号：US07572727B1
公开(公告)日：2009-08-11
申请号：US10934828
申请日：2004-09-02
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是一种半导体接触形成系统和方法。接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。导电材料（例如，钨）沉积在接触区域中。

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