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1. 发明授权

US07538026B1 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US07538026B1
公开(公告)日：2009-05-26
申请号：US11098262
申请日：2005-04-04
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

2. 发明授权

US08309457B2 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US08309457B2
公开(公告)日：2012-11-13
申请号：US13283076
申请日：2011-10-27
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

3. 发明申请

US20120045888A1 MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR 有权
标题翻译：多层低反射率硬掩模及其过程
公开(公告)号：US20120045888A1
公开(公告)日：2012-02-23
申请号：US13283076
申请日：2011-10-27
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

4. 发明授权

US08048797B2 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US08048797B2
公开(公告)日：2011-11-01
申请号：US12468715
申请日：2009-05-19
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

5. 发明申请

US20100009536A1 MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR 有权
标题翻译：多层低反射率硬掩模及其过程
公开(公告)号：US20100009536A1
公开(公告)日：2010-01-14
申请号：US12468715
申请日：2009-05-19
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/306 , G03F7/20
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

6. 发明授权

US06818141B1 Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines 有权
标题翻译： CVD双层ARC的应用是用于定义多晶硅字线之间的分解沟槽特征的硬掩模
公开(公告)号：US06818141B1
公开(公告)日：2004-11-16
申请号：US10166135
申请日：2002-06-10
申请人： Marina V. Plat , Kouros Ghandehari
发明人： Marina V. Plat , Kouros Ghandehari
IPC分类号： H01L2100
CPC分类号： H01L21/0276 , H01L21/32139
摘要： A method of removing organic anti-reflective coating (ARC) by ashing in an integrated circuit fabrication process can include providing an oxide-nitride-oxide (ONO) stack over a silicon substrate, providing a poly layer over the ONO stack, and patterning spaces in the poly layer using a patterned carbon bilayer ARC layer and a patterned hardmask layer. The patterned carbon bilayer ARC layer is ashed away before patterning spaces in the poly layer. Ashing the carbon bilayer ARC layer helps prevent damage to the ONO stack, improving the quality of the fabricated device.
摘要翻译：在集成电路制造工艺中通过灰化去除有机抗反射涂层（ARC）的方法可以包括在硅衬底上提供氧化物 - 氧化物 - 氧化物（ONO）堆叠，在ONO堆叠上提供多晶硅层，以及图案化空间在多层中使用图案化的碳双层ARC层和图案化的硬掩模层。在图案化多层中的空间之前，图案化的碳双层ARC层被去除。灰化碳双层ARC层有助于防止损坏ONO堆叠，从而提高制造设备的质量。

7. 发明授权

US06255125B1 Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer 失效
标题翻译：用于补偿半导体晶片生产中的临界尺寸变化的方法和装置
公开(公告)号：US06255125B1
公开(公告)日：2001-07-03
申请号：US09277093
申请日：1999-03-26
申请人： Regina T. Schmidt , Christopher A. Spence , Anna M. Minvielle , Marina V. Plat , Khanh B. Nguyen
发明人： Regina T. Schmidt , Christopher A. Spence , Anna M. Minvielle , Marina V. Plat , Khanh B. Nguyen
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques. Variations in critical dimension measurements taken from the test wafer as compared to desired predetermined line width measurements are compensated for prior to manufacturing the final production wafer so as to provide circuits with the desired electrical parameters.
摘要翻译：在制造最终生产晶片之前，制造了一系列测试晶片来分析和测试各种结构。每个测试晶片包括衬底，覆盖衬底的绝缘层和形成在绝缘层上的半导电膜层。膜层由例如多晶硅构成，并且具有基本对应于沉积在最终生产晶片上的膜层的厚度的预定厚度。蚀刻膜层以形成期望的结构图案，并注入掺杂剂以扩散掺杂剂原子。此后，优选使用电线宽度测量技术来获得结构的临界尺寸测量。在制造最终生产晶片之前补偿与期望的预定线宽测量值相比，从测试晶片获取的临界尺寸测量值的变化，以便为电路提供所需的电参数。

8. 发明授权

US07427457B1 Methods for designing grating structures for use in situ scatterometry to detect photoresist defects 有权
标题翻译：设计光栅结构的方法用于原位散射检测光刻胶缺陷
公开(公告)号：US07427457B1
公开(公告)日：2008-09-23
申请号：US10934277
申请日：2004-09-03
申请人： Marina V. Plat , Calvin T. Gabriel , Christopher F. Lyons , Anna M. Minvielle
发明人： Marina V. Plat , Calvin T. Gabriel , Christopher F. Lyons , Anna M. Minvielle
IPC分类号： G03F9/00
CPC分类号： G03F7/70783 , G03F1/44 , G03F7/70491 , G03F7/70533 , G03F7/7065
摘要： The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.
摘要翻译：本发明公开了一种用于在光刻工艺期间用于原位散射测量的光栅结构的系统和方法，用于检测光致抗蚀剂缺陷（例如，光致抗蚀剂侵蚀，图案崩溃或图案弯曲）。在一个实施例中，可以设计具有小于用于半导体器件的间距或临界尺寸的光栅结构。光栅结构的间距和临界尺寸可以变化。在另一个实施例中，本发明提供了原位散射测量过程和光刻工艺之间的反馈机制，以提供光刻胶缺陷的存在的早期警告。如果在晶片上检测到缺陷，则可以将晶片发送以进行再加工或重新图案化，从而避免报废整个晶片。

9. 发明授权

US07122455B1 Patterning with rigid organic under-layer 有权
标题翻译：图案与刚性有机底层
公开(公告)号：US07122455B1
公开(公告)日：2006-10-17
申请号：US10790567
申请日：2004-03-01
申请人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
发明人： Christopher F. Lyons , Marina V. Plat , Srikanteswara Dakshina-Murthy , Scott A. Bell , Cyrus E. Tabery
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , Y10S438/942 , Y10S438/947
摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.
摘要翻译：为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

10. 发明授权

US07015134B2 Method for reducing anti-reflective coating layer removal during removal of photoresist 失效
标题翻译：去除光刻胶时减少抗反射涂层去除的方法
公开(公告)号：US07015134B2
公开(公告)日：2006-03-21
申请号：US10079775
申请日：2002-02-19
申请人： Marina V. Plat , Angela T. Hui
发明人： Marina V. Plat , Angela T. Hui
IPC分类号： H01L21/4763
CPC分类号： H01L27/11526 , G03F7/091 , G03F7/40 , H01L21/0276 , H01L21/32139 , H01L27/105 , H01L27/11534
摘要： A method and system for providing a semiconductor device. The semiconductor device includes a first layer to be etched. The method and system include depositing an anti-reflective coating. At least a portion of the anti-reflective coating layer is on the first layer. The method and system also include patterning a resist layer. The resist layer includes a pattern having a plurality of apertures therein. The resist layer is for etching the first layer. A first portion of the first layer and a second portion of the anti-reflective coating layer are exposed by the pattern. The method and system also include etching the first portion of the first layer and the second portion of the anti-reflective coating layer and removing the resist layer utilizing a plasma etch. The anti-reflective coating layer is resistant to the plasma etch.
摘要翻译：一种用于提供半导体器件的方法和系统。半导体器件包括待蚀刻的第一层。该方法和系统包括沉积抗反射涂层。抗反射涂层的至少一部分在第一层上。该方法和系统还包括图案化抗蚀剂层。抗蚀剂层包括其中具有多个孔的图案。抗蚀剂层用于蚀刻第一层。第一层的第一部分和抗反射涂层的第二部分被图案曝光。该方法和系统还包括蚀刻第一层的第一部分和抗反射涂层的第二部分，并利用等离子体蚀刻去除抗蚀剂层。抗反射涂层耐等离子体蚀刻。

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