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1. 发明授权

US06894342B1 Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control 有权
标题翻译：用于防止存储单元中的紫外线辐射损伤的结构和方法，并改善接触式CD控制
公开(公告)号：US06894342B1
公开(公告)日：2005-05-17
申请号：US10460278
申请日：2003-06-12
申请人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
发明人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
IPC分类号： H01L21/336 , H01L21/8246 , H01L23/532 , H01L23/552 , H01L29/788
CPC分类号： H01L27/11568 , H01L23/53295 , H01L23/552 , H01L27/112 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over at least one memory cell and over the substrate. The structure further comprises a first antireflective coating layer situated over the interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises a second antireflective coating layer situated directly over the first anti reflective coating layer. Either the first antireflective coating layer or second antireflective coating layer must be a silicon-rich layer. The first antireflective coating layer and the second antireflective coating may form a UV radiation blocking layer having a UV transparency less than approximately 1.0 percent, for example.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。至少一个存储单元可以是例如SONOS闪存单元。该结构还包括位于至少一个存储器单元上方和衬底上方的层间电介质层。该结构还包括位于层间电介质层上的第一抗反射涂层。根据该示例性实施例，该结构还包括直接位于第一抗反射涂层上的第二抗反射涂层。第一抗反射涂层或第二抗反射涂层必须是富硅层。第一抗反射涂层和第二抗反射涂层可以形成例如UV透明度小于约1.0％的UV辐射阻挡层。

2. 发明授权

US06833581B1 Structure and method for preventing process-induced UV radiation damage in a memory cell 有权
标题翻译：用于防止在存储器单元中的加工诱导的UV辐射损伤的结构和方法
公开(公告)号：US06833581B1
公开(公告)日：2004-12-21
申请号：US10460282
申请日：2003-06-12
申请人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Kouros Ghandehari , Hirokazu Tokuno
发明人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Kouros Ghandehari , Hirokazu Tokuno
IPC分类号： H01L29788
CPC分类号： H01L27/11568 , H01L23/556 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell and may include a gate situated over an ONO stack. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer situated directly over the interlayer dielectric layer, where the UV radiation blocking layer is selected from the group consisting of silicon-rich oxide and silicon-rich nitride. The UV radiation blocking layer may have a thickness of between approximately 1500.0 Angstroms and approximately 2000.0 Angstroms, for example.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。至少一个存储器单元可以是例如闪速存储器单元，例如SONOS闪存单元，并且可以包括位于ONO堆栈上的门。所述结构还包括位于所述至少一个存储器单元上方并位于所述衬底之上的层间电介质层。根据该示例性实施例，该结构还包括直接位于层间电介质层上的UV辐射阻挡层，其中UV辐射阻挡层选自富硅氧化物和富含硅的氮化物。例如，UV辐射阻挡层的厚度可以在约1500.0埃和约2000.0埃之间。

3. 发明授权

US06765254B1 Structure and method for preventing UV radiation damage and increasing data retention in memory cells 有权
标题翻译：用于防止紫外线辐射损伤并增加记忆单元中数据保留的结构和方法
公开(公告)号：US06765254B1
公开(公告)日：2004-07-20
申请号：US10460279
申请日：2003-06-12
申请人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino , Tazrien Kamal , Cinti X. Chen
发明人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino , Tazrien Kamal , Cinti X. Chen
IPC分类号： H01L27108
CPC分类号： H01L27/115 , H01L23/552 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。至少一个存储单元可以是例如闪存单元，例如SONOS闪存单元。所述结构还包括位于所述至少一个存储器单元上方并位于所述衬底之上的层间电介质层。根据该示例性实施例，该结构还包括包含富含硅的TCS氮化物的UV辐射阻挡层。此外，氧化物覆盖层位于UV辐射阻挡层上。该结构还可以包括氧化物覆盖层上的抗反射涂层。层间电介质可以包括BPSG，并且氧化物覆盖层可以包含TEOS氧化物。

4. 发明申请

US20060214218A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214218A1
公开(公告)日：2006-09-28
申请号：US11258823
申请日：2005-10-25
申请人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
发明人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
IPC分类号： H01L29/792
CPC分类号： H01L21/76801 , H01L21/02129 , H01L21/022 , H01L21/3144 , H01L21/31625 , H01L21/76829 , H01L27/11568 , H01L29/40117 , H01L29/513
摘要： A semiconductor device includes a semiconductor substrate, an ONO film that is provided on the semiconductor substrate and has a contact hole, and an interlayer insulating film that is provided directly on the ONO film and contains phosphorus. The interlayer insulating film contains 4.5 wt % of phosphorus or more in an interface portion that interfaces with the ONO film. The interlayer insulating film comprises a first portion that contacts the ONO film, and a second portion provided on the first portion. The first portion has a phosphorus concentration more than that of the second portion.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上并具有接触孔的ONO膜，以及直接设置在ONO膜上并含有磷的层间绝缘膜。在与ONO膜接合的界面部分中，层间绝缘膜含有4.5重量％以上的磷。层间绝缘膜包括接触ONO膜的第一部分和设置在第一部分上的第二部分。第一部分的磷浓度大于第二部分的磷浓度。

5. 发明申请

US20070029604A1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
标题翻译：使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻
公开(公告)号：US20070029604A1
公开(公告)日：2007-02-08
申请号：US11546688
申请日：2006-10-12
申请人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
发明人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

6. 发明授权

US06642148B1 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist 失效
标题翻译： RELACS收缩方法应用于使用化学放大DUV型光致抗蚀剂的LDD或埋入式位线植入物的单面抗蚀剂掩模
公开(公告)号：US06642148B1
公开(公告)日：2003-11-04
申请号：US10126326
申请日：2002-04-19
申请人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
发明人： Kouros Ghandehari , Emmanuil H. Lingunis , Mark S. Chang , Angela Hui , Scott Bell , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/0274 , H01L21/31144 , H01L21/743 , H01L27/112 , H01L27/11521 , H01L27/11568
摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.
摘要翻译：本发明一般涉及一种在半导体衬底内形成渐变结的方法。在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

7. 发明申请

US20080096357A1 METHOD FOR MANUFACTURING A MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的方法
公开(公告)号：US20080096357A1
公开(公告)日：2008-04-24
申请号：US11551535
申请日：2006-10-20
申请人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
发明人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.
摘要翻译：一种用于制造存储器件的方法，其包括使用禁止存储器件之间的电荷耦合的间隙填充材料。提供了具有有源区和隔离区的半导体材料。在有源区上形成电荷俘获结构，在电荷俘获结构和隔离区上形成一层半导体材料。在半导体材料层上形成具有侧壁的掩模结构。间隔件邻近侧壁形成，并且半导体材料层被蚀刻以形成具有相对侧面的一个或多个导电条。一个或多个导电条形成在有源区上。在每个导电带的相对侧附近形成电介质材料。介电材料用作间隙填充材料。在一个或多个导电条上形成半导体材料层。

8. 发明授权

US08445372B2 Selective silicide formation using resist etch back 有权
标题翻译：使用抗蚀剂回蚀的选择性硅化物形成
公开(公告)号：US08445372B2
公开(公告)日：2013-05-21
申请号：US12644457
申请日：2009-12-22
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/285 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

9. 发明授权

US08022468B1 Ultraviolet radiation blocking interlayer dielectric 有权
标题翻译：紫外辐射阻挡层间电介质
公开(公告)号：US08022468B1
公开(公告)日：2011-09-20
申请号：US11091519
申请日：2005-03-29
申请人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
发明人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
IPC分类号： H01L29/66
CPC分类号： H01L27/11521 , H01L23/552 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.
摘要翻译：存储器件可以包括衬底，形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二介电层和形成在第二介电层上的控制栅极。存储器件还可以包括在控制栅极和衬底上形成的层间电介质，其中层间电介质包括对紫外线辐射基本不透明的材料。

10. 发明申请

US20090111265A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK 有权
标题翻译：选择性硅化物形成使用电阻蚀刻
公开(公告)号：US20090111265A1
公开(公告)日：2009-04-30
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

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