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1. 发明授权

US4530001A High voltage integrated semiconductor devices using a thermoplastic resin layer 失效
标题翻译：使用热塑性树脂层的高压集成半导体器件
公开(公告)号：US4530001A
公开(公告)日：1985-07-16
申请号：US302351
申请日：1981-09-15
申请人： Haruo Mori , Yasuo Ohno , Yutaka Ohta , Hiroshi Tanabe , Kotaro Kato
发明人： Haruo Mori , Yasuo Ohno , Yutaka Ohta , Hiroshi Tanabe , Kotaro Kato
IPC分类号： H01L21/312 , H01L21/58 , H01L21/762 , H01L21/764 , H01L23/14 , H01L27/00 , H01L27/12 , H01L29/06 , H01L23/48
CPC分类号： H01L24/83 , H01L21/312 , H01L21/764 , H01L23/145 , H01L24/29 , H01L27/1203 , H01L2224/2919 , H01L2224/8319 , H01L2224/8385 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/351
摘要： The semiconductor device comprises a semiconductor substrate, a plurality of spaced active elements, for example, of a planer type formed on one surface of the substrate, and a supporting plate bonded to the opposite surface of the substrate. A groove is cut through the substrate to reach the supporting plate for isolating the active elements.
摘要翻译：半导体器件包括半导体衬底，多个间隔开的有源元件，例如形成在衬底的一个表面上的平面型，以及与衬底相对的表面结合的支撑板。通过衬底切割凹槽以到达用于隔离有源元件的支撑板。

2. 发明授权

US4244000A PNPN Semiconductor switches 失效
标题翻译： PNPN半导体开关
公开(公告)号：US4244000A
公开(公告)日：1981-01-06
申请号：US96165
申请日：1979-11-20
申请人： Jun Ueda , Haruo Mori , Kazuo Hagimura , Kotaro Kato
发明人： Jun Ueda , Haruo Mori , Kazuo Hagimura , Kotaro Kato
IPC分类号： H01L27/144 , H01L29/10 , H01L29/74 , H01L29/747 , H01L29/749 , H01L31/111 , H03K17/082 , H03K17/725
CPC分类号： H01L29/747 , H01L27/1443 , H01L29/102 , H01L29/7408 , H01L29/742 , H01L31/1113 , H03K17/0824 , H03K17/725
摘要： A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.
摘要翻译：用于防止PNPN半导体开关的dV / dt错误操作的电路由半导体衬底，高电阻栅电极的表面上的电容代替。换句话说，这种电路通过对基本设计的轻微修改形成在基板的表面上，而不会减小芯片面积并且不隔离组件元件。

3. 发明授权

US4489340A PNPN Light sensitive semiconductor switch with phototransistor connected across inner base regions 失效
标题翻译： PNPN光敏半导体开关，光电晶体管连接在内部基极区域
公开(公告)号：US4489340A
公开(公告)日：1984-12-18
申请号：US228935
申请日：1981-01-28
申请人： Jun Ueda , Haruo Mori , Kazuo Hagimura , Hirokazu Tsukada , Kotaro Kato
发明人： Jun Ueda , Haruo Mori , Kazuo Hagimura , Hirokazu Tsukada , Kotaro Kato
IPC分类号： H01L27/144 , H01L31/111 , H04Q3/52 , H01L29/74
CPC分类号： H01L31/1113 , H01L27/1443 , H04Q3/521
摘要： A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.
摘要翻译：一种PNPN半导体开关，包括N型半导体衬底，形成在N型衬底的表面上的间隔开的第一和第二P型扩散区域，形成在第二P型扩散区域中的间隔开的第一和第二N型扩散区域，第一栅极绝缘层，形成在第一和第二N型扩散区域之间的第二P型扩散区域的表面上以覆盖其部分;形成在第一和第二N型扩散区域之间的第一栅极绝缘层上的第一栅电极，电阻区域，设置在所述第一栅极绝缘层上，所述电阻区域的与所述第一栅极电极相反一侧的一端，覆盖所述第一栅电极和所述电阻区域的第二栅极绝缘层，形成在所述第一栅极绝缘层的表面上的半绝缘层基板除了第一和第二P型扩散区域之外，覆盖半绝缘层的绝缘层，P栅极电极与第二P型扩散区域和第二N型扩散区域连接的第二栅电极，形成在第一栅极电极上方的第二栅极绝缘层上的第二栅电极，连接到第一N型扩散区域的阴极电极，连接到第一P型扩散区域和第二栅电极的阳极电极和形成在第一栅极绝缘层正下方以及第一和第二N型扩散区域之间的高电阻区域。

4. 发明授权

US4004162A Clock signal reproducing network for PCM signal reception 失效
标题翻译：用于PCM信号接收的时钟信号再现网络
公开(公告)号：US4004162A
公开(公告)日：1977-01-18
申请号：US651369
申请日：1976-01-22
申请人： Kotaro Kato , Haruki Takai
发明人： Kotaro Kato , Haruki Takai
IPC分类号： H04L1/00 , H03K3/86 , H03K5/00 , H03L7/00 , H03L7/06 , H04B7/155 , H04J3/06 , H04L5/22 , H04L7/02 , H04L7/027 , H03K3/78
CPC分类号： H04L7/027
摘要： A clock signal reproducing network for PCM signal reception is capable of reproducing a clock signal even if the clock component is absent in the input digital signal for a prolonged period of time. The network includes a clock signal component extracting circuit and a bandpass filter for extracting and band-limiting the clock signal component in a received digital signal. An envelope detection circuit and a level decision circuit are connected to receive the output of the bandpass filter to provide a control signal to an output switching circuit. When the amplitude of the envelope of the filter output is high, the output of the bandpass filter is used directly as a reproduced clock signal. When the amplitude of the envelope is low, the clock signal obtained immediately before the filter amplitude becomes small is derived repeatedly from a delay circuit as a substituted clock signal.
摘要翻译：即使长时间在输入数字信号中不存在时钟分量，用于PCM信号接收的时钟信号再现网络能够再现时钟信号。网络包括时钟信号分量提取电路和带通滤波器，用于提取和限制接收的数字信号中的时钟信号分量。连接包络检测电路和电平判定电路以接收带通滤波器的输出以向输出开关电路提供控制信号。当滤波器输出的包络的幅度高时，带通滤波器的输出被直接用作再现的时钟信号。当包络的振幅低时，紧接在滤波器幅度变小之前获得的时钟信号作为替代时钟信号从延迟电路重复地导出。

5. 发明授权

US4639548A Digital communication system including an error correcting encoder/decoder and a scrambler/descrambler 失效
标题翻译：数字通信系统包括纠错编码器/解码器和加扰器/解扰器
公开(公告)号：US4639548A
公开(公告)日：1987-01-27
申请号：US718725
申请日：1985-04-01
申请人： Goro Oshima , Kotaro Kato
发明人： Goro Oshima , Kotaro Kato
IPC分类号： H04L1/00 , H03M13/00 , H03M13/33 , H04L7/00 , H04L25/03 , H04L9/00
CPC分类号： H04L25/03872 , H03M13/00 , H03M13/33
摘要： An error correction code data communication system scrambles and descrambles both non-coded data and coded data by using substantially the same code process at the opposite ends of a transmission path. The frequency of the occurrence of an error correction pulse in a decoder is monitored to set up synchronization for descrambling. The transmitter includes an encoder for adding a correction code to a data signal to be transmitted, and a scrambler for randomizing the data signal. The receiver includes a descrambler for descrambling the data signal which was randomized by the scrambler, and a decoder for correcting a code error responsive to the error correction code. The scrambler modulo 2 adds an output of a random signal generator to both an input data signal and an output data signal. The descrambler modulo 2 adds an output of a second random signal generator to both an input data signal and an output data signal.
摘要翻译：错误校正码数据通信系统通过在传输路径的相对端使用基本上相同的码过程来加扰和解扰非编码数据和编码数据。监视解码器中发生纠错脉冲的频率，以建立用于解扰的同步。发射机包括用于将校正码添加到要发射的数据信号的编码器，以及用于使数据信号随机化的加扰器。该接收机包括一个解扰器，用于对由扰频器进行随机化的数据信号进行解扰，以及解码器，用于响应纠错码校正码错误。加扰器模2将随机信号发生器的输出添加到输入数据信号和输出数据信号。解扰器模2将第二随机信号发生器的输出添加到输入数据信号和输出数据信号。

6. 发明授权

US4339817A Clock recovery circuit for burst communications systems 失效
标题翻译：用于突发通信系统的时钟恢复电路
公开(公告)号：US4339817A
公开(公告)日：1982-07-13
申请号：US183333
申请日：1980-09-02
申请人： Masaharu Hata , Kotaro Kato
发明人： Masaharu Hata , Kotaro Kato
IPC分类号： H04J3/06 , H04B7/155 , H04L7/027 , H04L7/033 , H04L7/10 , H04L27/22 , H04L7/00 , H04J6/00
CPC分类号： H04L7/033
摘要： A clock recovery circuit includes an oscillator having a frequency which is substantially equal to the clock frequency of bursts which are transmitted from a plurality of stations. A phase difference detector circuit responds to phase differences between clock signals extracted from each of the bursts and from the output from the oscillator. An averaging circuit averages the detected phase differences over an interval which is designated by a first control signal. A memory circuit stores the averaged phase difference in response to a second control signal and reads out the stored phase differences in response to a third control signal. A control circuit generates the first to third control signals in response to the output from the oscillator. A phase shift circuit shifts the phase of the output from the oscillator, based on the phase difference read out from the memory circuit. This generates and recovers the original clock pulse signal. The clock of the first burst corresponding to the stored phase difference is used as the clock for a second burst from the same station which transmits the first burst.
摘要翻译：时钟恢复电路包括具有基本上等于从多个站发送的突发的时钟频率的频率的振荡器。相位差检测器电路响应从每个突发提取的时钟信号与来自振荡器的输出的相位差。平均电路在由第一控制信号指定的间隔上对检测到的相位差进行平均。存储电路响应于第二控制信号存储平均的相位差，并响应于第三控制信号读出存储的相位差。控制电路响应于来自振荡器的输出而产生第一至第三控制信号。基于从存储器电路读出的相位差，相移电路使振荡器的输出的相位移位。这将产生并恢复原始时钟脉冲信号。对应于所存储的相位差的第一脉冲串的时钟被用作来自发送第一脉冲串的同一电台的第二脉冲串的时钟。

7. 发明授权

US5188881A Thermosensitive stencil paper 失效
标题翻译：热敏蜡纸
公开(公告)号：US5188881A
公开(公告)日：1993-02-23
申请号：US717908
申请日：1991-06-20
申请人： Shoichi Sugiyama , Fumiaki Arai , Masayasu Nonogaki , Yuji Natori , Hideyuki Yamaguchi , Hitoshi Ueda , Hiroshi Tomita , Kotaro Kato
发明人： Shoichi Sugiyama , Fumiaki Arai , Masayasu Nonogaki , Yuji Natori , Hideyuki Yamaguchi , Hitoshi Ueda , Hiroshi Tomita , Kotaro Kato
IPC分类号： B41N1/24
CPC分类号： B41N1/245 , Y10S428/913 , Y10T428/24372 , Y10T428/31786 , Y10T428/31913 , Y10T428/3192
摘要： A thermosensitive stencil paper is composed of a substrate and a thermoplastic resin film formed thereon, which thermoplastic resin film has projections in the surface portion thereof, with a printing roughness (R.sub.p) of 2.2 to 5.0 .mu.m, which is a physical quantity proportional to the average depth of the depressions in the surface portion thereof pressed against a standard surface.
摘要翻译：热敏蜡纸由形成在其上的基材和热塑性树脂膜组成，热塑性树脂膜在其表面部分具有突起，印刷粗糙度（R p）为2.2〜5.0μm，其物理量与其表面部分中的凹陷的平均深度压在标准表面上。

8. 发明授权

US4393573A Method of manufacturing semiconductor device provided with complementary semiconductor elements 失效
标题翻译：制造具有互补半导体元件的半导体器件的制造方法
公开(公告)号：US4393573A
公开(公告)日：1983-07-19
申请号：US181357
申请日：1980-08-26
申请人： Kotaro Kato , Tetsuma Sakurai
发明人： Kotaro Kato , Tetsuma Sakurai
IPC分类号： H01L21/762 , H01L21/8228 , H01L27/08 , H01L27/082 , H01L27/092 , H01L21/223
CPC分类号： H01L27/0928 , H01L21/76297 , H01L21/82285 , H01L27/0817 , H01L27/0826
摘要： The semiconductor device is provided with semiconductor elements having the complementary characteristics and high breakdown strength. These semiconductor elements are formed in N and P islands respectively each having an inverted frustum shape.Surfaces of the frustum are inclined by an angle determined by semiconductor crystal structure. Side and bottom surfaces of the islands are formed adjacent to an insulating layer and both islands are supported part from the polycrystalline semiconductor layer. All side and bottom surfaces of the islands adjacent the insulating layer are made of high impurity substance of the same type as respective islands.
摘要翻译：半导体器件设置有具有互补特性和高击穿强度的半导体元件。这些半导体元件分别形成在具有倒立的截头锥形状的N和P岛中。平截头体的表面倾斜由半导体晶体结构确定的角度。岛的侧表面和底表面邻近绝缘层形成，并且两个岛都是来自多晶半导体层的支撑部分。与绝缘层相邻的岛的所有侧表面和底表面由与各岛相同类型的高杂质物质制成。

9. 发明授权

US4210996A Trimming method for resistance value of polycrystalline silicon resistors especially used as semiconductor integrated circuit resistors 失效
标题翻译：多晶硅电阻的电阻值修正方法，特别用作半导体集成电路电阻
公开(公告)号：US4210996A
公开(公告)日：1980-07-08
申请号：US900300
申请日：1978-04-26
申请人： Yoshihito Amemiya , Kotaro Kato
发明人： Yoshihito Amemiya , Kotaro Kato
IPC分类号： H01L27/04 , H01C17/22 , H01L21/02 , H01L21/326 , H01L21/822 , H01L27/01
CPC分类号： H01L28/20 , H01L21/326 , Y10S148/055 , Y10T29/49082 , Y10T29/49099
摘要： Current having a density higher than a critical value is passed through a polycrystalline resistor doped with impurities at a concentration higher than a critical value to decreasingly correct the initial value of the resistance, thereby trimming the resistance value of the resistor. When the resistor is used in a semiconductor integrated circuit, the current is passed through the existing (not additional) terminals of the integrated circuit.
摘要翻译：具有高于临界值的密度的电流通过掺杂有高于临界值的杂质的多晶电阻器，以减少校正电阻的初始值，从而调整电阻器的电阻值。当半导体集成电路中使用电阻时，电流通过集成电路的现有（非附加）端子。

10. 发明授权

US3962860A Quartz crystal timepiece 失效
标题翻译：石英水晶钟表
公开(公告)号：US3962860A
公开(公告)日：1976-06-15
申请号：US502185
申请日：1974-08-30
申请人： Kotaro Kato , Makoto Morimoto
发明人： Kotaro Kato , Makoto Morimoto
IPC分类号： G04G3/00 , G04F5/06 , G04G17/04 , H03B5/32 , H05K1/02 , H05K1/18 , G04C3/00 , H03B5/30
CPC分类号： G04G17/04 , G04F5/063 , H05K1/0237 , H05K1/18
摘要： A quartz crystal timepiece incorporating a vibrator unit is disclosed. The vibrator unit is hermetically sealed in a case on which a condenser is fixed and the condenser compensates the oscillating frequency of said vibrator unit to a predetermined center frequency by suitably selecting the capacitance of the condenser after measuring the natural frequency of the vibrator unit. Then there is no need to adjust each vibrator unit to the predetermined center frequency during assembling process.
摘要翻译：公开了一种并入振子单元的石英晶体钟表。振动器单元被密封在其上固定有电容器的壳体中，并且电容器通过在测量振动器单元的固有频率之后适当地选择电容器来补偿所述振动器单元的振荡频率至预定的中心频率。然后在组装过程中不需要将每个振动器单元调整到预定的中心频率。

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