专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07525162B2 Orientation-optimized PFETS in CMOS devices employing dual stress liners 失效
标题翻译：采用双重应力衬垫的CMOS器件中的取向优化PFETS
公开(公告)号：US07525162B2
公开(公告)日：2009-04-28
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 1 0] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译：在具有（110）表面取向且位于衬底中的硅层上提供PFET。设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。当PFET通道的方向与平面内[1 10]晶体方向的方位角之间时，主压缩纵向应变和次级拉伸横向应力的净效益最大化（110）硅层为约25°至约55°。

2. 发明申请

US20090065867A1 ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS 失效
标题翻译：使用双应力衬片的CMOS器件中的方位优化PFET
公开(公告)号：US20090065867A1
公开(公告)日：2009-03-12
申请号：US11850933
申请日：2007-09-06
申请人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
发明人： Haizhou Yin , Katherine L. Saenger , Chun-Yung Sung , Kai Xiu
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/7843
摘要： A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 10] crystallographic direction in the (110) silicon layer is from about 25° to about 55.
摘要翻译：在具有（110）表面取向且位于衬底中的硅层上提供PFET。设置在PFET的栅极和源极/漏极区域上的压应力衬垫沿着PFET沟道的方向产生初级纵向压缩应变。设置在横向邻近PFET的至少一个NFET上的拉伸应力衬垫沿着NFET通道的方向产生初级纵向拉伸应变。来自至少一个NFET拉伸衬套的二次应力场在PFET通道中产生有益的横向拉伸应力。当PFET通道的方向和平面内[1 10]晶体方向的方位角在（（））时，主压缩纵向应变和次拉伸横向应力的最大优点是最大化， 110）硅层为约25°至约55°。

3. 发明授权

US08236636B2 Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same 有权
标题翻译：具有减少边界缺陷的混合取向半导体结构及其形成方法
公开(公告)号：US08236636B2
公开(公告)日：2012-08-07
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

4. 发明申请

US20100203708A1 AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES 有权
标题翻译：用于混合定向衬底的拟合/调制再结晶方法
公开(公告)号：US20100203708A1
公开(公告)日：2010-08-12
申请号：US12767261
申请日：2010-04-26
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/26 , H01L21/322
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

5. 发明授权

US07704852B2 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07704852B2
公开(公告)日：2010-04-27
申请号：US11871694
申请日：2007-10-12
申请人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

6. 发明授权

US07691733B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
标题翻译：激光加工方法用于封闭几何中的无边缘无缺陷固相外延
公开(公告)号：US07691733B2
公开(公告)日：2010-04-06
申请号：US12062749
申请日：2008-04-04
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

7. 发明授权

US07960263B2 Amorphization/templated recrystallization method for hybrid orientation substrates 有权
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07960263B2
公开(公告)日：2011-06-14
申请号：US12767261
申请日：2010-04-26
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

8. 发明授权

US07465992B2 Field effect transistor with mixed-crystal-orientation channel and source/drain regions 有权
标题翻译：具有混晶取向沟道和源极/漏极区的场效应晶体管
公开(公告)号：US07465992B2
公开(公告)日：2008-12-16
申请号：US11116053
申请日：2005-04-27
申请人： Joel P. Desouza , Devendra K. Sadana , Katherine L. Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
发明人： Joel P. Desouza , Devendra K. Sadana , Katherine L. Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/7624 , H01L21/823807 , H01L21/8258 , H01L27/0605 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/66636 , H01L29/7833
摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.
摘要翻译：混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET）以半导体方向设置，其对于空穴迁移率是最佳的。本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。可以并入其中可并入这些新的FET的混合基板及其制造方法。

9. 发明申请

US20110086473A1 HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME 有权
标题翻译：具有减少边界缺陷的混合方向半导体结构及其形成方法
公开(公告)号：US20110086473A1
公开(公告)日：2011-04-14
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

10. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式