专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080286917A1 LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS 失效
标题翻译：激光加工方法，用于在限位几何中进行无边缘固定相外延激光
公开(公告)号：US20080286917A1
公开(公告)日：2008-11-20
申请号：US12062749
申请日：2008-04-04
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/265 , H01L21/8238
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

2. 发明授权

US07547616B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
标题翻译：激光加工方法用于封闭几何中的无边缘无缺陷固相外延
公开(公告)号：US07547616B2
公开(公告)日：2009-06-16
申请号：US11406122
申请日：2006-04-18
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

3. 发明授权

US07691733B2 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
标题翻译：激光加工方法用于封闭几何中的无边缘无缺陷固相外延
公开(公告)号：US07691733B2
公开(公告)日：2010-04-06
申请号：US12062749
申请日：2008-04-04
申请人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith E. Fogel , Kam-Leung Lee , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变：熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

4. 发明申请

US20060275971A1 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
公开(公告)号：US20060275971A1
公开(公告)日：2006-12-07
申请号：US11406122
申请日：2006-04-18
申请人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/26
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

5. 发明授权

US06437406B1 Super-halo formation in FETs 失效
标题翻译： FET中的超卤素形成
公开(公告)号：US06437406B1
公开(公告)日：2002-08-20
申请号：US09692093
申请日：2000-10-19
申请人： Kam-Leung Lee
发明人： Kam-Leung Lee
IPC分类号： H01L2701
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/6659
摘要： A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.
摘要翻译：半导体衬底在结处具有与掺杂剂原子的至少一个PN结。在结点处的非掺杂剂提供间隙捕获以防止退火过程中的扩散。在制造这一过程中，将非掺杂剂扩散阻挡层例如C，N，Si，F等注入半导体器件的“卤素”区域，例如，二极管，双极晶体管或CMOSFET。这与较低的退火预算（“Spike退火”）结合使得可以产生更陡的光晕掺杂物分布。本发明在栅极长度小于约50nm的CMOSFET中是特别有用的。

6. 发明授权

US07074684B2 Elevated source drain disposable spacer CMOS 失效
公开(公告)号：US07074684B2
公开(公告)日：2006-07-11
申请号：US10894219
申请日：2004-07-19
申请人： Ronnen A. Roy , Cyril Cabral, Jr. , Christian Lavoie , Kam-Leung Lee
发明人： Ronnen A. Roy , Cyril Cabral, Jr. , Christian Lavoie , Kam-Leung Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66492 , H01L21/26513 , H01L21/2652 , H01L21/26586 , H01L21/28035 , H01L21/28114 , H01L21/28518 , H01L21/28525 , H01L21/324 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6659 , Y10S438/924
摘要： In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

7. 发明授权

US06369434B1 Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors 有权
标题翻译：氮共同注入形成p型金属氧化物半导体场效应晶体管的浅结延长
公开(公告)号：US06369434B1
公开(公告)日：2002-04-09
申请号：US09363742
申请日：1999-07-30
申请人： Kai Chen , Scott W. Crowder , Liang-Kai Han , Michael J. Hargrove , Kam-Leung Lee , Hung Y. Ng
发明人： Kai Chen , Scott W. Crowder , Liang-Kai Han , Michael J. Hargrove , Kam-Leung Lee , Hung Y. Ng
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/36 , H01L29/7833
摘要： A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.
摘要翻译：具有非常浅的p结延伸的p型MOSFET。半导体器件通过产生从衬底表面延伸到预定深度优选小于约800的注入氮离子的层而在衬底上产生。栅电极用作掩模，使得氮注入不会在栅极下方延伸。硼也被植入到与氮注入相当的程度和深度，从而形成非常浅的p结延伸，即使在热处理之后仍保持约束在氮层内。因此，在半导体材料中的氮和硼的容纳层中产生具有非常浅的p结延伸的pMOSFET。

8. 发明申请

US20130334693A1 RAISED SILICIDE CONTACT 有权
标题翻译：提高硅胶接触
公开(公告)号：US20130334693A1
公开(公告)日：2013-12-19
申请号：US13525401
申请日：2012-06-18
申请人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
发明人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/02063 , H01L21/28525 , H01L21/76814 , H01L21/823814 , H01L23/485 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
摘要翻译：一种用于形成硅化物接触的方法，所述方法包括使用气体簇注入技术沉积硅层，所述气体簇注入技术加速硅原子簇，使得它们穿过硅化物的顶表面上的表面氧化物; 将包括硅层的硅化物加热到约300℃至约950℃的温度，并在惰性气氛中保持约0.1毫秒至约600秒的温度，从而使来自硅层的硅部分地与剩余的硅化物部分地反应形成在含硅衬底中; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。

9. 发明申请

US20100327375A1 SHALLOW EXTENSION REGIONS HAVING ABRUPT EXTENSION JUNCTIONS 失效
标题翻译：具有缓冲延伸功能的扩展区域
公开(公告)号：US20100327375A1
公开(公告)日：2010-12-30
申请号：US12491819
申请日：2009-06-25
申请人： Kam-Leung Lee , Paul A. Ronsheim
发明人： Kam-Leung Lee , Paul A. Ronsheim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/324 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds.
摘要翻译：提供一种形成半导体器件的方法，其包括在衬底顶部形成栅极结构并将衬底中的掺杂剂从衬底的上表面注入到10nm或更小的深度。在随后的步骤中，以1200℃至1400℃的峰值温度和1毫秒至5毫秒的保持时间段进行退火。

10. 发明申请

US20050145941A1 High performance strained silicon FinFETs device and method for forming same 有权
标题翻译：高性能应变硅FinFET器件及其形成方法
公开(公告)号：US20050145941A1
公开(公告)日：2005-07-07
申请号：US10751916
申请日：2004-01-07
申请人： Stephen Bedell , Kevin Chan , Dureseti Chidambarrao , Silke Christiansen , Jack Chu , Anthony Domenicucci , Kam-Leung Lee , Anda Mocuta , John Ott , Qiqing Ouyang
发明人： Stephen Bedell , Kevin Chan , Dureseti Chidambarrao , Silke Christiansen , Jack Chu , Anthony Domenicucci , Kam-Leung Lee , Anda Mocuta , John Ott , Qiqing Ouyang
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变的Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式