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1. 发明授权

US06908806B2 Gate metal recess for oxidation protection and parasitic capacitance reduction 失效
标题翻译：栅极金属凹槽用于氧化保护和寄生电容降低
公开(公告)号：US06908806B2
公开(公告)日：2005-06-21
申请号：US10355726
申请日：2003-01-31
申请人： Haining Yang , Ramachandra Divakaruni , Oleg Gluschenkov , Rajeev Malik , Hongwen Yan , Ravikumar Ramachandran
发明人： Haining Yang , Ramachandra Divakaruni , Oleg Gluschenkov , Rajeev Malik , Hongwen Yan , Ravikumar Ramachandran
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/76838
摘要： A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有包括栅极叠层侧壁的栅极叠层结构，栅叠层结构具有一个或多个包含栅极金属的金属层。栅极金属通过化学蚀刻从栅极堆叠侧壁凹入。门堆叠结构的栅极金属被选择性地氧化以形成至少部分地填充凹部的金属氧化物。

2. 发明授权

US07030012B2 Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM 失效
标题翻译：在垂直DRAM中制造钨/多晶硅字线结构的方法
公开(公告)号：US07030012B2
公开(公告)日：2006-04-18
申请号：US10708530
申请日：2004-03-10
申请人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
发明人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
IPC分类号： H01L21/44
CPC分类号： H01L27/10894 , H01L27/10861 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.
摘要翻译：包括至少一个半导体存储器阵列区域和包括支撑区域的逻辑电路的集成电路器件通过以下步骤形成。在阵列区域上形成牺牲多晶硅层。在器件上形成覆盖栅极氧化物层。在字线位于的阵列区域和逻辑电路所在的支撑区域中形成厚多晶硅沉积物。仅在阵列区域中去除厚的多晶硅层，栅极氧化物层和牺牲多晶硅层。然后在阵列区域和支撑区域中沉积薄多晶硅层。接着在薄多晶硅层上沉积至少包含元素金属层部分的金属导体涂层。然后分别在阵列区域和支撑区域中形成字线和基极。

3. 发明申请

US20050202672A1 METHOD FOR MANUFACTURING TUNGSTEN/POLYSILICON WORD LINE STRUCTURE IN VERTICAL DRAM AND DEVICE MANUFACTURED THEREBY 失效
标题翻译：在垂直DRAM中制造TUNGSTEN / POLYSILICON WORD LINE结构的方法及其制造的器件
公开(公告)号：US20050202672A1
公开(公告)日：2005-09-15
申请号：US10708530
申请日：2004-03-10
申请人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
发明人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44 , H01L21/8234 , H01L21/8242 , H01L23/52 , H01L27/088 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L27/10894 , H01L27/10861 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprised of at least one semiconductor memory array and logic circuits. The memory array includes electrically conductive word lines. The logic circuits include logic transistors with electrically conductive gates. The gates of the logic transistors and the word lines are composed of polysilicon and a metal layer. The metal layer is thicker than the polysilicon layer in the word lines; and the metal layer is thinner than the polysilicon layer in the gates of the logic transistors.
摘要翻译：一种由至少一个半导体存储器阵列和逻辑电路组成的集成电路。存储器阵列包括导电字线。逻辑电路包括具有导电栅极的逻辑晶体管。逻辑晶体管和字线的栅极由多晶硅和金属层组成。金属层比字线中的多晶硅层厚; 并且金属层比逻辑晶体管的栅极中的多晶硅层薄。

4. 发明授权

US06509226B1 Process for protecting array top oxide 有权
标题翻译：保护阵列顶部氧化物的方法
公开(公告)号：US06509226B1
公开(公告)日：2003-01-21
申请号：US09670741
申请日：2000-09-27
申请人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
发明人： Venkatachalam C. Jaiprakash , Jack Mandelman , Ramachandra Divakaruni , Rajeev Malik , Mihel Seitz
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.
摘要翻译：包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。沉积栅极堆叠并图案化，并且该工艺继续完成。

5. 发明授权

US06541810B2 Modified vertical MOSFET and methods of formation thereof 失效
标题翻译：改进的垂直MOSFET及其形成方法
公开(公告)号：US06541810B2
公开(公告)日：2003-04-01
申请号：US09896741
申请日：2001-06-29
申请人： Ramachandra Divakaruni , Prakash Dev , Rajeev Malik , Larry Nesbit
发明人： Ramachandra Divakaruni , Prakash Dev , Rajeev Malik , Larry Nesbit
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891
摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.
摘要翻译：用于形成动态随机存取存储器的垂直MOSFET结构包括包括一个或多个氮化硅间隔物的栅堆叠结构; 设置在阵列沟槽中的垂直栅极多晶硅区域，其中所述垂直栅极多晶硅区域包括一个或多个氮化硅间隔物; 位线扩散区; 与阵列沟槽接壤的浅沟槽隔离区; 并且其中栅极堆叠结构设置在垂直栅极多晶硅区域上，使得栅极堆叠结构和垂直栅极多晶硅区域的氮化硅间隔物与位线扩散区域和浅沟槽隔离区域形成无边界接触。垂直栅极多晶硅通过氮化物间隔物从位线扩散和浅沟槽隔离区域隔离，这提供了减少的位线电容并且减少了位线扩散到垂直栅极短路的入射。

6. 发明授权

US06358867B1 Orientation independent oxidation of silicon 有权
标题翻译：硅取向独立氧化
公开(公告)号：US06358867B1
公开(公告)日：2002-03-19
申请号：US09596097
申请日：2000-06-16
申请人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
发明人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C30B29/06 , C30B33/00 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28176 , H01L21/28211 , H01L21/31662 , H01L21/76202 , H01L29/513 , H01L29/518 , Y10S438/973
摘要： A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.
摘要翻译：根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中硅表面具有硅晶体的至少两个不同晶体取向的衬底。形成氧化表面的原子氧（O）。通过使原子氧与表面反应，在表面上形成氧化物，同时形成表面上氧化物的基本均匀的厚度。

7. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

8. 发明申请

US20080108228A1 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 有权
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：US20080108228A1
公开(公告)日：2008-05-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

9. 发明授权

US07732270B2 Device having enhanced stress state and related methods 有权
标题翻译：具有增强的应力状态和相关方法的装置
公开(公告)号：US07732270B2
公开(公告)日：2010-06-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

10. 发明申请

US20060128091A1 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 有权
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：US20060128091A1
公开(公告)日：2006-06-15
申请号：US10905025
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

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