专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06541810B2 Modified vertical MOSFET and methods of formation thereof 失效
标题翻译：改进的垂直MOSFET及其形成方法
公开(公告)号：US06541810B2
公开(公告)日：2003-04-01
申请号：US09896741
申请日：2001-06-29
申请人： Ramachandra Divakaruni , Prakash Dev , Rajeev Malik , Larry Nesbit
发明人： Ramachandra Divakaruni , Prakash Dev , Rajeev Malik , Larry Nesbit
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891
摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.
摘要翻译：用于形成动态随机存取存储器的垂直MOSFET结构包括包括一个或多个氮化硅间隔物的栅堆叠结构; 设置在阵列沟槽中的垂直栅极多晶硅区域，其中所述垂直栅极多晶硅区域包括一个或多个氮化硅间隔物; 位线扩散区; 与阵列沟槽接壤的浅沟槽隔离区; 并且其中栅极堆叠结构设置在垂直栅极多晶硅区域上，使得栅极堆叠结构和垂直栅极多晶硅区域的氮化硅间隔物与位线扩散区域和浅沟槽隔离区域形成无边界接触。垂直栅极多晶硅通过氮化物间隔物从位线扩散和浅沟槽隔离区域隔离，这提供了减少的位线电容并且减少了位线扩散到垂直栅极短路的入射。

2. 发明申请

US20050014332A1 Method to improve bitline contact formation using a line mask 审中-公开
标题翻译：使用线掩模改善位线接触形成的方法
公开(公告)号：US20050014332A1
公开(公告)日：2005-01-20
申请号：US10619884
申请日：2003-07-15
申请人： Michael Maldei , Johnathan Faltermeier , David Dobuzinsky , Prakash Dev , Thomas Rupp
发明人： Michael Maldei , Johnathan Faltermeier , David Dobuzinsky , Prakash Dev , Thomas Rupp
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/76895 , H01L27/10864 , H01L27/10888
摘要： A semiconductor device is fabricated to have improved bitline contact formation. Polysilicon is deposited between gate contacts that connect to transistors of DRAM memory cells. The polysilicon covers the gate contacts and continues to cover the gate contacts during subsequent processing steps. A bitline of, e.g., tungsten, is deposited so that it contacts at least a portion of the polysilicon, thereby providing electrical contact with the DRAM transistors.
摘要翻译：制造半导体器件具有改进的位线接触形成。多晶硅沉积在连接到DRAM存储单元的晶体管的栅极触点之间。多晶硅覆盖栅极触点，并在后续处理步骤中继续覆盖栅极触点。沉积例如钨的位线，使得其接触多晶硅的至少一部分，由此提供与DRAM晶体管的电接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式