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1. 再颁专利

USRE36663E Planarized selective tungsten metallization system 失效
标题翻译：平面选择性钨金属化系统
公开(公告)号：USRE36663E
公开(公告)日：2000-04-18
申请号：US473812
申请日：1995-06-07
申请人： Gregory C. Smith , Thomas D. Bonifield
发明人： Gregory C. Smith , Thomas D. Bonifield
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/00 , H01L21/02 , H01L21/283 , H01L21/90
CPC分类号： H01L21/32051 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76879 , H01L21/76807
摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).
摘要翻译：在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和进入孔（20）。此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面第二电介质层（30）。

2. 发明授权

US5055423A Planarized selective tungsten metallization system 失效
标题翻译：平面选择性钨金属化系统
公开(公告)号：US5055423A
公开(公告)日：1991-10-08
申请号：US383304
申请日：1989-07-18
申请人： Gregory C. Smith , Thomas D. Bonifield
发明人： Gregory C. Smith , Thomas D. Bonifield
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/32051 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76879 , H01L21/76807
摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).
摘要翻译：在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和进入孔（20）。此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面第二电介质层（30）。

3. 发明授权

US08436475B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08436475B2
公开(公告)日：2013-05-07
申请号：US13444508
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.
摘要翻译：半导体器件包括：集成电路（IC）管芯，其包括衬底;以及多个通过衬底通孔（TSV），其穿过衬底延伸到突出的整体尖端，并且部分地被电介质衬垫覆盖并部分地从电介质暴露衬垫。金属层位于IC芯片的底表面上，物理地连接多个TSV，并物理和电连接到连接TSV的第一金属突出尖端。

4. 发明申请

US20080308904A1 P-DOPED REGION WITH IMPROVED ABRUPTNESS 审中-公开
标题翻译：具有改善性破坏的P区域
公开(公告)号：US20080308904A1
公开(公告)日：2008-12-18
申请号：US11763497
申请日：2007-06-15
申请人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
发明人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
IPC分类号： H01L21/425 , H01L29/36
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/268 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/66068 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底中提供C原子。该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

5. 发明授权

US07344985B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07344985B2
公开(公告)日：2008-03-18
申请号：US11551374
申请日：2006-10-20
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

6. 发明授权

US08154134B2 Packaged electronic devices with face-up die having TSV connection to leads and die pad 有权
标题翻译：封装的电子设备具有面向上的裸片，TSV连接到引线和裸片焊盘
公开(公告)号：US08154134B2
公开(公告)日：2012-04-10
申请号：US12463184
申请日：2009-05-08
申请人： Thomas D. Bonifield , Gary P. Morrison , Rajiv Dunne , Satyendra S. Chauhan , Masood Murtuza
发明人： Thomas D. Bonifield , Gary P. Morrison , Rajiv Dunne , Satyendra S. Chauhan , Masood Murtuza
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/495 , H01L23/04
CPC分类号： H01L23/49575 , H01L23/481 , H01L23/49513 , H01L24/12 , H01L24/31 , H01L24/83 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13024 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/2929 , H01L2224/29339 , H01L2224/83851 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19104 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.
摘要翻译：封装的电子设备包括引线框架，引线框架包括管芯焊盘，围绕管芯焊盘的第一，第二和第三引脚引脚。在引线框架上以面朝上的配置组装IC芯片。 IC芯片包括具有有源顶表面和底表面的衬底，其中顶表面包括集成电路，其包括输入焊盘，输出焊盘，电源焊盘和接地焊盘，以及多个贯穿衬底通孔（TSV），其包括导电填充材料和电介质衬垫。 TSV将输入焊盘耦合到第一引脚引脚，输出焊盘连接到第二引脚引脚，电源焊盘连接到第三引脚引脚或芯片焊盘的一部分。第四TSV将耦合到接地节点的焊盘耦合到管芯焊盘或用于分离管芯焊盘的芯片焊盘的一部分。

7. 发明授权

US07833895B2 TSVS having chemically exposed TSV tips for integrated circuit devices 有权
标题翻译： TSVS具有用于集成电路器件的化学暴露的TSV尖端
公开(公告)号：US07833895B2
公开(公告)日：2010-11-16
申请号：US12463282
申请日：2009-05-08
申请人： Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
发明人： Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
摘要翻译：一种用于制造IC的方法，包括从第一至第
一通孔（TSV）和IC及其电子组件。提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。化学蚀刻通常是三步化学蚀刻。

8. 发明授权

US07511350B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07511350B2
公开(公告)日：2009-03-31
申请号：US12018313
申请日：2008-01-23
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

9. 发明授权

US07211516B2 Nickel silicide including indium and a method of manufacture therefor 有权
公开(公告)号：US07211516B2
公开(公告)日：2007-05-01
申请号：US11096660
申请日：2005-04-01
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

10. 发明授权

US06709974B2 Method of preventing seam defects in isolated lines 有权
标题翻译：防止隔离线缝合缺陷的方法
公开(公告)号：US06709974B2
公开(公告)日：2004-03-23
申请号：US10322763
申请日：2002-12-19
申请人： David Permana , Jiong-Ping Lu , Albert Cheng , Jeff A. West , Brock W. Fairchild , Scott A. Johannesmeyer , Chris M. Bowles , Thomas D. Bonifield , Rajesh Tiwari
发明人： David Permana , Jiong-Ping Lu , Albert Cheng , Jeff A. West , Brock W. Fairchild , Scott A. Johannesmeyer , Chris M. Bowles , Thomas D. Bonifield , Rajesh Tiwari
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/3212 , H01L21/7684
摘要： A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.
摘要翻译：提供了一种在CMP工艺期间防止0.3微米或更小的狭窄隔离线上的接缝缺陷的方法。解决方案是改变与金属层相同的层上的虚拟金属结构的特征的尺寸，以使其宽度为约0.6微米或更小，使得在电镀期间，特征中的沉积速率类似于窄的，隔离的线条。虚拟金属结构的密度，形状和接近度通过防止电蚀腐蚀来防止CMP加工过程中的接缝缺陷。

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