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1. 发明申请

US20080308904A1 P-DOPED REGION WITH IMPROVED ABRUPTNESS 审中-公开
标题翻译：具有改善性破坏的P区域
公开(公告)号：US20080308904A1
公开(公告)日：2008-12-18
申请号：US11763497
申请日：2007-06-15
申请人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
发明人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
IPC分类号： H01L21/425 , H01L29/36
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/268 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/66068 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底中提供C原子。该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

2. 发明授权

US07678637B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US07678637B2
公开(公告)日：2010-03-16
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

3. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

4. 发明申请

US20100133624A1 CMOS Fabrication Process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US20100133624A1
公开(公告)日：2010-06-03
申请号：US12696215
申请日：2010-01-29
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

5. 发明授权

US07557022B2 Implantation of carbon and/or fluorine in NMOS fabrication 有权
标题翻译：在NMOS制造中植入碳和/或氟
公开(公告)号：US07557022B2
公开(公告)日：2009-07-07
申请号：US11451919
申请日：2006-06-13
申请人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
发明人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
IPC分类号： H01L21/425
CPC分类号： H01L21/2658 , H01L21/26506 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.
摘要翻译：公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F2）中的至少一种与砷，磷和锑中的至少一种的注入组合。掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

6. 发明授权

US07344985B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07344985B2
公开(公告)日：2008-03-18
申请号：US11551374
申请日：2006-10-20
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

7. 发明申请

US20070287274A1 Implantation of carbon and/or fluorine in NMOS fabrication 有权
标题翻译：在NMOS制造中植入碳和/或氟
公开(公告)号：US20070287274A1
公开(公告)日：2007-12-13
申请号：US11451919
申请日：2006-06-13
申请人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
发明人： Mahalingam Nandakumar , Amitabh Jain , Lahir Shaik Adam
IPC分类号： H01L21/425
CPC分类号： H01L21/2658 , H01L21/26506 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.
摘要翻译：公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F 2 O 2）中的至少一种与砷，磷和锑中的至少一种的注入相结合。掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

8. 发明授权

US08558310B2 Indium, carbon and halogen doping for PMOS transistors 有权
公开(公告)号：US08558310B2
公开(公告)日：2013-10-15
申请号：US12967105
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/02 , H01L21/8234
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L29/66477 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

9. 发明授权

US08125035B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US08125035B2
公开(公告)日：2012-02-28
申请号：US12696215
申请日：2010-01-29
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

10. 发明申请

US20110147854A1 INDIUM, CARBON AND HALOGEN DOPING FOR PMOS TRANSISTORS 有权
标题翻译：用于PMOS晶体管的印刷，碳和阴极掺杂
公开(公告)号：US20110147854A1
公开(公告)日：2011-06-23
申请号：US12967105
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L29/66477 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.
摘要翻译：形成具有至少一个PMOS晶体管的集成电路（IC）的方法包括执行PLDD注入，包括共注入铟，碳和卤素，以及硼物种，以在具有半导体表面的衬底中建立源极/漏极延伸区域栅极结构的任一侧包括形成在半导体表面上的栅极电介质上的栅电极。进行源极和漏极注入以建立源极/漏极区域，其中源极/漏极区域远离源极/漏极延伸区域远离栅极结构。在源极和漏极注入之后进行源极/漏极退火。共注入物可以选择性地仅提供到核心PMOS晶体管，并且该方法可以包括超高温退火，例如在PLDD注入之后的激光退火。

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