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1. 发明授权

US08436475B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08436475B2
公开(公告)日：2013-05-07
申请号：US13444508
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.
摘要翻译：半导体器件包括：集成电路（IC）管芯，其包括衬底;以及多个通过衬底通孔（TSV），其穿过衬底延伸到突出的整体尖端，并且部分地被电介质衬垫覆盖并部分地从电介质暴露衬垫。金属层位于IC芯片的底表面上，物理地连接多个TSV，并物理和电连接到连接TSV的第一金属突出尖端。

2. 发明申请

US20100109128A1 Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage 有权
标题翻译：用于提高半导体器件抗锯齿损伤鲁棒性的裂纹偏转器结构
公开(公告)号：US20100109128A1
公开(公告)日：2010-05-06
申请号：US12613175
申请日：2009-11-05
申请人： Jeffrey Alan WEST , Thomas D. BONIFIELD , Basab CHATTERJEE
发明人： Jeffrey Alan WEST , Thomas D. BONIFIELD , Basab CHATTERJEE
IPC分类号： H01L23/58 , H01L21/71
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
摘要翻译：一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。连续金属层不延伸经过连续接触和连续通孔。连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面划线或裂纹偏转划痕。

3. 发明申请

US20080308904A1 P-DOPED REGION WITH IMPROVED ABRUPTNESS 审中-公开
标题翻译：具有改善性破坏的P区域
公开(公告)号：US20080308904A1
公开(公告)日：2008-12-18
申请号：US11763497
申请日：2007-06-15
申请人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
发明人： P. R. Chidambaram , Srinivasan Chakravarthi , Mahalingam Nandakumar , Manoj Mehrotra , Amitabh Jain , Thomas D. Bonifield
IPC分类号： H01L21/425 , H01L29/36
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/268 , H01L21/324 , H01L21/823814 , H01L29/165 , H01L29/66068 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底中提供C原子。该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

4. 发明授权

US07344985B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07344985B2
公开(公告)日：2008-03-18
申请号：US11551374
申请日：2006-10-20
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

5. 再颁专利

USRE36663E Planarized selective tungsten metallization system 失效
标题翻译：平面选择性钨金属化系统
公开(公告)号：USRE36663E
公开(公告)日：2000-04-18
申请号：US473812
申请日：1995-06-07
申请人： Gregory C. Smith , Thomas D. Bonifield
发明人： Gregory C. Smith , Thomas D. Bonifield
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/00 , H01L21/02 , H01L21/283 , H01L21/90
CPC分类号： H01L21/32051 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76879 , H01L21/76807
摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).
摘要翻译：在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和进入孔（20）。此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面第二电介质层（30）。

6. 发明授权

US08431481B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08431481B2
公开(公告)日：2013-04-30
申请号：US13444545
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L21/4763
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.
摘要翻译：形成半导体器件的方法包括：集成电路（IC）管芯，其具有表面的衬底。至少一个通过衬底通孔（TSV）通过衬底形成为包括侧壁和远端的突出的整体尖端。在IC芯片的底面上形成有金属层，突出整体尖端的侧壁和远端形成。完成至少一个功能电路的制造，该至少一个功能电路包括在半导体的顶表面上的至少一个接地焊盘，其中接地焊盘耦合到所述TSV。

7. 发明申请

US20120202321A1 IC Device Having Low Resistance TSV Comprising Ground Connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US20120202321A1
公开(公告)日：2012-08-09
申请号：US13444545
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L21/60 , H01L21/58
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.
摘要翻译：形成半导体器件的方法包括：集成电路（IC）管芯，其具有表面的衬底。至少一个通过衬底通孔（TSV）通过衬底形成为包括侧壁和远端的突出的整体尖端。在IC芯片的底面上形成有金属层，突出整体尖端的侧壁和远端形成。完成至少一个功能电路的制造，该至少一个功能电路包括在半导体的顶表面上的至少一个接地焊盘，其中接地焊盘耦合到所述TSV。

8. 发明授权

US08178976B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08178976B2
公开(公告)日：2012-05-15
申请号：US12463086
申请日：2009-05-08
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.
摘要翻译：半导体器件包括包括衬底的集成电路（IC）裸片，以及至少一个穿过衬底延伸穿过衬底通过包括侧壁和远端的突出整体尖端的贯穿衬底通孔（TSV）。突出的整体尖端具有1至50μm的尖端高度。金属层位于IC芯片的底表面，并且突出的整体尖端的侧壁和远端。半导体器件可以包括包括TSV的IC管芯和诸如引线框架的封装衬底，其中IC管芯包括金属层和导电管芯附着粘合剂层，例如焊料填充聚合物，其中焊料布置在电互连网络中，在金属层和引线框架的管芯焊盘之间。

9. 发明申请

US20110018107A1 TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices 审中-公开
标题翻译： TSVS具有化学暴露的集成电路器件的TSV提示
公开(公告)号：US20110018107A1
公开(公告)日：2011-01-27
申请号：US12899754
申请日：2010-10-07
申请人： Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
发明人： Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
摘要翻译：一种用于制造IC的方法，包括从第一至第
一通孔（TSV）和IC及其电子组件。提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。化学蚀刻通常是三步化学蚀刻。

10. 发明申请

US20090278238A1 TSVS HAVING CHEMICALLY EXPOSED TSV TIPS FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：具有化学电路设备的化学物理TSV
公开(公告)号：US20090278238A1
公开(公告)日：2009-11-12
申请号：US12463282
申请日：2009-05-08
申请人： THOMAS D. BONIFIELD , BRIAN E. GOODLIN , MONA M. EISSA
发明人： THOMAS D. BONIFIELD , BRIAN E. GOODLIN , MONA M. EISSA
IPC分类号： H01L23/52 , H01L21/306 , H01L21/304
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
摘要翻译：一种用于制造IC的方法，包括从第一至第
一通孔（TSV）和IC及其电子组件。提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。化学蚀刻通常是三步化学蚀刻。

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