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1. 发明申请

US20130082385A1 DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER 有权
标题翻译：具有热膨胀层数的系数
公开(公告)号：US20130082385A1
公开(公告)日：2013-04-04
申请号：US13251498
申请日：2011-10-03
申请人： BRIAN K. KIRKPATRICK , RAJESH TIWARI
发明人： BRIAN K. KIRKPATRICK , RAJESH TIWARI
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76879 , H01L23/481 , H01L23/5329 , H01L23/53295 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.
摘要翻译：半导体管芯包括：衬底，其包括被配置为提供电路功能的电路元件的顶面。模具包括至少一个多层结构，其包括具有第一CTE的第一材料，包括具有第二CTE的金属的第二材料，其中第二CTE高于第一CTE。热膨胀系数（CTE）渐变层至少包括位于第一材料和第二材料之间的电介质部分，其具有面向第一材料的第一侧面和面向第二材料的第二侧面。 CTE分级层包括横跨其厚度的非恒定组成轮廓，其提供了从第一侧向第二侧增加CTE的分级CTE。多层结构可以是穿过衬底的厚度的贯穿衬底通孔（TSV）。

2. 发明授权

US06941242B2 Versatile system for variance-based data analysis 有权
标题翻译：用于基于方差数据分析的多功能系统
公开(公告)号：US06941242B2
公开(公告)日：2005-09-06
申请号：US10676399
申请日：2003-10-01
申请人： Nital S. Patel , Rajesh Tiwari
发明人： Nital S. Patel , Rajesh Tiwari
IPC分类号： G06F17/18
CPC分类号： G06F17/18
摘要： The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements of a primary device characteristic from a representative cross-section of a population of devices. The system provides a modeling function, from which is determined a variance for each measurement—forming a corresponding compilation of variances (200). The compilation of variances is evaluated for discontinuities (300), to identify a discontinuity within the compilation of variances. This discontinuity is utilized to determine a demarcation (302) between accurate and inaccurate measurement data.
摘要翻译：本发明定义了用于分析工业测量数据的精度的通用系统。本发明的系统从一组设备的代表性横截面编译主要设备特性的测量结果。该系统提供建模功能，由此确定每个测量的方差 - 形成相应的方差汇编（200）。对不连续性（300）评估方差的汇编，以确定方差汇编中的不连续性。该不连续性用于确定准确和不精确的测量数据之间的分界（302）。

3. 发明申请

US20050059189A1 Dual depth trench termination method for improving Cu-based interconnect integrity 有权
标题翻译：用于改善Cu基互连完整性的双深沟槽端接方法
公开(公告)号：US20050059189A1
公开(公告)日：2005-03-17
申请号：US10663948
申请日：2003-09-16
申请人： Rajesh Tiwari , Russell Fields , Scott Boddicker , Andrew Kim
发明人： Rajesh Tiwari , Russell Fields , Scott Boddicker , Andrew Kim
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76808
摘要： A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge α of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150), (160) to form the interconnect line.
摘要翻译：在低K电介质（100）中，在也形成在低K电介质层（100）中的多个通孔（120）上形成沟槽。通孔的距离小于XV，并且沟槽的边缘比最接近沟槽边缘的通孔的边缘α大于XTO。沟槽和通孔随后填充铜（150），（160）以形成互连线。

4. 发明申请

US20210368316A1 PATRON SERVICE METHOD UTILIZING NEAR-FIELD COMMUNICATION TAG IDENTIFIERS 有权
公开(公告)号：US20210368316A1
公开(公告)日：2021-11-25
申请号：US16882310
申请日：2020-05-22
申请人： Rajesh Tiwari , Archana Deshpande , Archit Peshave
发明人： Rajesh Tiwari , Archana Deshpande , Archit Peshave
IPC分类号： H04W4/80 , H04W4/021 , H04W4/33 , G06F3/0482 , G06F3/0481 , G06Q20/20 , G06Q50/12 , H04W12/06 , H04W8/26
摘要： A near-field communication (“NFC”) tag identifier (ID) associated with an establishment obtain by scanning an NFC tag at a location in the establishment using a wireless device of a patron is received. Login credentials associated with the patron and the wireless device are received. A location of the patron in the establishment is determined from the login credentials associated with the patron and the wireless device, and from the NFC tag ID. An available service of the establishment is communicated to the wireless device of the patron based on the login credentials associated with the patron and the wireless device, and from the NFC tag ID. The identified location is associated with exact order items so the service staff is able to keep track of an order made by the patron.

5. 发明申请

US20130113103A1 DEVICE HAVING TSVs WITH GETTERING LAYER LATERAL TO TSV TIPS 审中-公开
标题翻译：具有入口层的TSV的设备到TSV TIPS
公开(公告)号：US20130113103A1
公开(公告)日：2013-05-09
申请号：US13489219
申请日：2012-06-05
申请人： JEFFREY A. WEST , RAJESH TIWARI
发明人： JEFFREY A. WEST , RAJESH TIWARI
IPC分类号： H01L23/532 , H01L21/302
CPC分类号： H01L23/481 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %.
摘要翻译：集成电路（IC）包括具有顶侧半导体表面的衬底，其包括被配置为提供功能和底部表面的有源电路。多个贯穿衬底通孔（TSV）从顶侧半导体表面延伸到底部表面以提供突出的TSV尖端。 TSV包括外电介质衬垫，在电介质衬垫上包含扩散阻挡层的金属和在包含阻挡层的金属上的金属填料。电介质金属吸气层（MGL）位于突出的TSV尖端的侧面和侧壁上的底部表面上。 MGL包括选自0.1至10原子％的平均浓度的至少一种选自卤素或15族元素的金属吸杂剂。

6. 发明申请

US20130062736A1 POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS 审中-公开
标题翻译：后聚合物通过提取物穿透基底
公开(公告)号：US20130062736A1
公开(公告)日：2013-03-14
申请号：US13228594
申请日：2011-09-09
申请人： JEFFREY E. BRIGHTON , JEFFREY A. WEST , RAJESH TIWARI
发明人： JEFFREY E. BRIGHTON , JEFFREY A. WEST , RAJESH TIWARI
IPC分类号： H01L29/45 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/76898 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.
摘要翻译：一种形成半导体管芯的方法包括在具有包括有源电路和底部基底的顶面的衬底的底部上形成聚合物层或聚合物的前体，以及多个穿通基底通孔（TSV）。 TSV具有包括至少介电衬垫和延伸到从底部突出的TSV尖端的内金属芯的衬垫。聚合物或前体和衬里层覆盖多个TSV尖端，并且聚合物或前体层位于底部的TSV尖端之间。将聚合物或前体和衬垫从TSV尖端的顶部上移除以露出内部金属芯。

7. 发明授权

US07519905B2 Automatic formatting and validating of text for a markup language graphical user interface 有权
标题翻译：自动格式化和验证标记语言图形用户界面的文本
公开(公告)号：US07519905B2
公开(公告)日：2009-04-14
申请号：US10649198
申请日：2003-08-27
申请人： Panagiotis Kougiouris , Chip Bering , Rajesh Tiwari
发明人： Panagiotis Kougiouris , Chip Bering , Rajesh Tiwari
IPC分类号： G06F17/00 , G09G5/02
CPC分类号： G06F17/243 , G06F17/211 , G06F17/2247 , G06F17/2725
摘要： A system and method for automatically performing validation and/or formatting procedures for a graphical user interface (GUI) described in a markup language file. The GUI markup language description may comprise descriptions of various types of GUI elements for which text is to be validated/formatted, such as form fields, tables, hypertext links, etc. The markup language file may include various custom markup language attributes in order to automatically validate/format text for a GUI element. Validation/formatting procedures for GUI elements may thus be based on custom markup language attributes and are managed by a manager that is automatically instantiated when the application parses the markup language file. This manager interfaces to receive programmatic events that trigger various types of formatting/validating operations to be performed on the GUI elements.
摘要翻译：用于自动执行标记语言文件中描述的图形用户界面（GUI）的验证和/或格式化过程的系统和方法。 GUI标记语言描述可以包括对要对其进行验证/格式化的文本的各种类型的GUI元素的描述，诸如表单域，表格，超文本链接等。标记语言文件可以包括各种自定义标记语言属性，以便自动验证/格式化GUI元素的文本。因此，GUI元素的验证/格式化过程可以基于自定义标记语言属性，并且由管理器管理，该管理器在应用程序解析标记语言文件时自动实例化。该管理器接口接收程序化事件，触发在GUI元素上执行的各种类型的格式化/验证操作。

8. 发明授权

US08618661B2 Die having coefficient of thermal expansion graded layer 有权
标题翻译：模具具有热膨胀系数梯度层
公开(公告)号：US08618661B2
公开(公告)日：2013-12-31
申请号：US13251498
申请日：2011-10-03
申请人： Brian K. Kirkpatrick , Rajesh Tiwari
发明人： Brian K. Kirkpatrick , Rajesh Tiwari
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76879 , H01L23/481 , H01L23/5329 , H01L23/53295 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.
摘要翻译：半导体管芯包括：衬底，其包括被配置为提供电路功能的电路元件的顶面。模具包括至少一个多层结构，其包括具有第一CTE的第一材料，包括具有第二CTE的金属的第二材料，其中第二CTE高于第一CTE。热膨胀系数（CTE）渐变层至少包括位于第一材料和第二材料之间的电介质部分，其具有面向第一材料的第一侧面和面向第二材料的第二侧面。 CTE分级层包括横跨其厚度的非恒定组成轮廓，其提供了从第一侧向第二侧增加CTE的分级CTE。多层结构可以是穿过衬底的厚度的贯穿衬底通孔（TSV）。

9. 发明授权

US06444569B1 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process 有权
公开(公告)号：US06444569B1
公开(公告)日：2002-09-03
申请号：US09835276
申请日：2001-04-16
申请人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
发明人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
IPC分类号： H01L214763
摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

10. 发明授权

US06274478B1 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process 有权
标题翻译：使用多台板化学机械抛光（CMP）工艺形成铜互连的方法
公开(公告)号：US06274478B1
公开(公告)日：2001-08-14
申请号：US09352136
申请日：1999-07-13
申请人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
发明人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.
摘要翻译：铜互连抛光工艺通过使用第一压板抛光（17）铜（63）的体积厚度开始。然后使用第二压板来去除（19）薄的剩余界面铜层以暴露阻挡膜（61）。计算机控制（21）监测第一和第二压板的抛光时间并调整这些时间以提高晶片的吞吐量。一个或多个压板和/或晶片在界面铜抛光剂和阻隔抛光剂之间漂洗（20），以减少淤浆交叉污染。然后使用第三压板和浆料抛光掉屏障（61）的暴露部分以完成铜互连结构的抛光。使用含有防腐蚀液体的储存罐将晶片排队，直到后续的擦洗操作（25）。使用基本上无光的擦洗操作（25）用于减少洗涤器的干燥室中的铜的光伏诱发的腐蚀。

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