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    • 3. 发明授权
      US06472715B1 Reduced soft error rate (SER) construction for integrated circuit structures 有权
    • Reduced soft error rate (SER) construction for integrated circuit structures
    • 降低集成电路结构的软错误率（SER）结构
    • US06472715B1
    • 2002-10-29
    • US09675109
    • 2000-09-28
    • Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
    • Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
    • H01L2976
    • H01L21/823892 , H01L27/11
    • An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.
    • 诸如SRAM结构的集成电路结构，其中软错误率被降低包括形成在半导体衬底中的集成电路结构，其中至少一个N沟道晶体管被构建在邻近一个或多个深N阱的P阱中， 高压电源和深N阱从衬底的表面向下延伸到衬底中的至少等于α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软错误的深度的深度。 对于具有一个或多个常规深度不超过约0.5μm的N个阱的0.25μmSRAM设计，α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软误差的深度为1至3μm 。 因此，0.25μmSRAM设计的深N阱从衬底表面向下延伸至少约1um，优选至少约2μm的距离。 在优选实施例中，衬底的注入以形成本发明的改进的SRAM的深N阱以将导致分段的方式进行，即，使得包括深N阱的掺杂体积在其基极处变宽 。 这样扩大的基底深N阱将增加收集由α粒子与基底碰撞产生的电子的机会。 可以通过增加植入能量或通过相对于植入物束的轴线倾斜衬底同时植入衬底以形成深N阱来形成具有加宽基底的该深N阱。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06442061B1 Single channel four transistor SRAM 有权
    • Single channel four transistor SRAM
    • 单通道四晶体管SRAM
    • US06442061B1
    • 2002-08-27
    • US09783653
    • 2001-02-14
    • Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
    • Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
    • G11C1100
    • G11C11/412 , H01L27/11
    • A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
    • 根据本发明的形成存储单元的方法。 第一栅极晶体管由第一晶体管形成。 第一栅极晶体管具有第一厚度的栅极氧化物。 第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。 第一栅极晶体管的栅极电连接到存储器单元使能线。 第二栅极晶体管也由第一晶体管形成。 第二栅极晶体管还具有第一厚度的栅极氧化物。 第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。 第二通栅晶体管的栅极电连接到存储单元使能线。 第一状态节点晶体管也由第一晶体管类型形成。 第一状态节点晶体管具有第二厚度的栅极氧化物。 第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。 第一状态节点的门电连接到第二状态节点。 第二状态节点晶体管也由第一晶体管类型形成。 第二状态节点晶体管也具有第二厚度的栅极氧化物。 第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。 第二状态节点的门电连接到第一状态节点。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US07190185B2 Methodology to measure many more transistors on the same test area 有权
    • Methodology to measure many more transistors on the same test area
    • 在同一测试区域测量更多晶体管的方法
    • US07190185B2
    • 2007-03-13
    • US10696320
    • 2003-10-29
    • Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
    • Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
    • G01R31/02
    • G01R31/2884
    • A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.
    • 提供诸如晶体管的测试结构的测试方法被布置成多行。 逻辑电路控制要测量哪一行。 增量器接收触发信号并用作地址加法器。 每当触发信号从0上升到1时，增量器的输出增加1.加法器的输出作为输入到解码器的地址。 解码器连接到测试结构的行。 优选地，每个测试结构包含由该信号（即解码器的输出）控制的控制电路。 如果测试结构是晶体管，则可以使用公共栅极，源极和阱单独施加对每个晶体管的偏置，并且可以使用单独的漏极节点进行测量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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