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1. 发明申请

US20050093560A1 New methodology to measure many more transistors on the same test area 有权
标题翻译：在同一测试区域测量更多晶体管的新方法
公开(公告)号：US20050093560A1
公开(公告)日：2005-05-05
申请号：US10696320
申请日：2003-10-29
申请人： Franklin Duan , Minxuan Liu , John Walker , Nabil Mansour , Carl Monzel
发明人： Franklin Duan , Minxuan Liu , John Walker , Nabil Mansour , Carl Monzel
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2884
摘要： A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.
摘要翻译：提供诸如晶体管的测试结构的测试方法被布置成多行。逻辑电路控制要测量哪一行。增量器接收触发信号并用作地址加法器。每当触发信号从0上升到1时，增量器的输出增加1.加法器的输出作为输入到解码器的地址。解码器连接到测试结构的行。优选地，每个测试结构包含由该信号（即解码器的输出）控制的控制电路。如果测试结构是晶体管，则可以使用公共栅极，源极和阱单独施加对每个晶体管的偏置，并且可以使用单独的漏极节点进行测量。

2. 发明授权

US07190185B2 Methodology to measure many more transistors on the same test area 有权
标题翻译：在同一测试区域测量更多晶体管的方法
公开(公告)号：US07190185B2
公开(公告)日：2007-03-13
申请号：US10696320
申请日：2003-10-29
申请人： Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
发明人： Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.
摘要翻译：提供诸如晶体管的测试结构的测试方法被布置成多行。逻辑电路控制要测量哪一行。增量器接收触发信号并用作地址加法器。每当触发信号从0上升到1时，增量器的输出增加1.加法器的输出作为输入到解码器的地址。解码器连接到测试结构的行。优选地，每个测试结构包含由该信号（即解码器的输出）控制的控制电路。如果测试结构是晶体管，则可以使用公共栅极，源极和阱单独施加对每个晶体管的偏置，并且可以使用单独的漏极节点进行测量。

3. 发明申请

US20130163357A1 Quantifying the Read and Write Margins of Memory Bit Cells 有权
标题翻译：量化存储位单元的读和写裕量
公开(公告)号：US20130163357A1
公开(公告)日：2013-06-27
申请号：US13337902
申请日：2011-12-27
申请人： Myron Buer , Carl Monzel , Yifei Zhang
发明人： Myron Buer , Carl Monzel , Yifei Zhang
IPC分类号： G11C29/00 , G11C5/14
CPC分类号： G11C11/413 , G11C8/08 , G11C11/41 , G11C11/419 , G11C29/50 , G11C2029/1202 , G11C2029/5002
摘要： Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.
摘要翻译：在筛选老化效应期间，通过在额定工作电压下操作外围电路来防止外围电路故障导致的损耗，同时筛选用于老化效应的存储器阵列。包括一个或多个存储位单元的集成电路包括改变施加到位单元的电源轨的电压和施加到字线驱动器的电压相对于彼此的电压的电路，以便于改进对读和写余量的屏蔽。在正常操作中，字线驱动器和位单元的电源轨标称地相同。在写裕度测试模式下，字线驱动器的电源轨上的电压低于位单元的电源轨上的电压。在读取余量测试模式中，字线驱动器的电源轨上的电压高于位单元的电源轨上的电压。

4. 发明授权

US08705268B2 Quantifying the read and write margins of memory bit cells 有权
标题翻译：量化存储位单元的读和写余量
公开(公告)号：US08705268B2
公开(公告)日：2014-04-22
申请号：US13337902
申请日：2011-12-27
申请人： Myron Buer , Carl Monzel , Yifei Zhang
发明人： Myron Buer , Carl Monzel , Yifei Zhang
IPC分类号： G11C11/00 , G11C29/00 , G11C5/14 , G11C8/00
CPC分类号： G11C11/413 , G11C8/08 , G11C11/41 , G11C11/419 , G11C29/50 , G11C2029/1202 , G11C2029/5002
摘要： Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.
摘要翻译：在筛选老化效应期间，通过在额定工作电压下操作外围电路来防止外围电路故障导致的损耗，同时筛选用于老化效应的存储器阵列。包括一个或多个存储位单元的集成电路包括改变施加到位单元的电源轨的电压和施加到字线驱动器的电压相对于彼此的电压的电路，以便于改进对读和写余量的屏蔽。在正常操作中，字线驱动器和位单元的电源轨标称地相同。在写裕度测试模式下，字线驱动器的电源轨上的电压低于位单元的电源轨上的电压。在读取余量测试模式中，字线驱动器的电源轨上的电压高于位单元的电源轨上的电压。

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