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1. 发明授权

US07157795B1 Composite tantalum nitride/tantalum copper capping layer 有权
标题翻译：复合氮化钽/钽铜覆盖层
公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
申请人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译：通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

2. 发明授权

US06454916B1 Selective electroplating with direct contact chemical polishing 失效
标题翻译：选择性电镀与直接接触化学抛光
公开(公告)号：US06454916B1
公开(公告)日：2002-09-24
申请号：US09477810
申请日：2000-01-05
申请人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
发明人： Fei Wang , Steven C. Avanzino , Darrell M. Erb
IPC分类号： C25D1700
CPC分类号： C25D5/22 , B23H5/08 , C25D7/12 , C25D17/001
摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
摘要翻译：沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

3. 发明授权

US06169034A Chemically removable Cu CMP slurry abrasive 有权
标题翻译：化学去除Cu CMP浆料研磨剂
公开(公告)号：US06169034A
公开(公告)日：2001-01-02
申请号：US09199352
申请日：1998-11-25
申请人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
发明人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
IPC分类号： H01L21461
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463
摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.
摘要翻译：在CMP期间对Cu金属化的磨损降低，并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化，并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸，磷酸，硼酸或氟硼酸除去残留的氧化镁颗粒。

4. 发明授权

US6140239A Chemically removable Cu CMP slurry abrasive 有权
标题翻译：化学去除Cu CMP浆料研磨剂
公开(公告)号：US6140239A
公开(公告)日：2000-10-31
申请号：US199266
申请日：1998-11-25
申请人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
发明人： Steven C. Avanzino , Darrell M. Erb , Diana M. Schonauer , Kai Yang
IPC分类号： H01L21/02 , H01L21/306 , H01L21/321 , H01L21/304
CPC分类号： H01L21/02074 , H01L21/3212
摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of iron oxide particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing iron oxide particles and removing residual iron oxide particles after CMP with an organic acid, such as oxalic acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, boric or fluoroboric acid.
摘要翻译：在CMP期间对Cu金属化的磨损减少，并且通过使用含有在稀酸中具有高溶解度的氧化铁颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。实施方案包括用含有氧化铁颗粒的浆料和CMP之后用有机酸如草酸或乙酸除去残留的氧化铁颗粒，或稀释的无机酸如盐酸，硼酸或氟硼酸的CMP Cu金属化。

5. 发明授权

US06756306B2 Low temperature dielectric deposition to improve copper electromigration performance 有权
标题翻译：低温介电沉积提高铜电迁移性能
公开(公告)号：US06756306B2
公开(公告)日：2004-06-29
申请号：US10334387
申请日：2002-12-30
申请人： Steven C. Avanzino , Darrell M. Erb
发明人： Steven C. Avanzino , Darrell M. Erb
IPC分类号： H01L2144
CPC分类号： H01L21/02118 , H01L21/02167 , H01L21/02271 , H01L21/312 , H01L21/314 , H01L21/76801 , H01L21/76829 , H01L21/76834
摘要： The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
摘要翻译：通过用于在金属化图案上沉积钝化层的化学气相沉积工艺来增强镶嵌在介电材料层的表面中的平坦化金属化特征（例如铜）的可靠性和电迁移寿命，其包括保持在上部处于或低于第一温度的金属化特征的表面是预先沉积在其上的抑制膜。抑制膜基本上抑制在第一温度以下的金属化特征的表面上形成氧化物层。钝化层沉积在高于第一温度的第二温度下发生，使得去除抑制膜和钝化层的形成之间的时间间隔足够短，从而基本上抑制金属特征表面上的氧化物的形成。

6. 发明授权

US06500754B1 Anneal hillock suppression method in integrated circuit interconnects 有权
标题翻译：集成电路互连中的退火小丘抑制方法
公开(公告)号：US06500754B1
公开(公告)日：2002-12-31
申请号：US09999661
申请日：2001-10-31
申请人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
发明人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
IPC分类号： H01L214763
CPC分类号： H01L21/76883
摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.
摘要翻译：因此，提供了具有半导体器件的半导体衬底的集成电路和制造方法。在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。在导体芯和阻挡层平坦化之前，在400℃及以上的高温下进行半导体衬底的退火以刺激晶粒生长。在平坦化之后，随后的钝化层或覆盖层的高温沉积将不会导致晶粒生长并且抑制小丘。

7. 发明授权

US06319834B1 Method and apparatus for improved planarity metallization by electroplating and CMP 有权
标题翻译：通过电镀和CMP改善平面度金属化的方法和装置
公开(公告)号：US06319834B1
公开(公告)日：2001-11-20
申请号：US09639812
申请日：2000-08-17
申请人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
发明人： Darrell M. Erb , Steven C. Avanzino , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/3212 , H01L21/2885 , H01L21/7684 , H01L21/76877 , H01L21/76879
摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.
摘要翻译：通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。

8. 发明授权

US06727592B1 Copper interconnect with improved barrier layer 有权
标题翻译：铜互连具有改进的阻挡层
公开(公告)号：US06727592B1
公开(公告)日：2004-04-27
申请号：US10079515
申请日：2002-02-22
申请人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
发明人： Christy Mei-Chu Woo , John E. Sanchez , Darrell M. Erb , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76868 , H01L21/76871 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
摘要翻译： Cu互连，例如通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃阻挡层，沉积种子层，然后用Cu填充开口。实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

9. 发明授权

US4745454A High capacity semiconductor capacitance device structure 失效
标题翻译：大容量半导体电容器件结构
公开(公告)号：US4745454A
公开(公告)日：1988-05-17
申请号：US926600
申请日：1986-11-03
申请人： Darrell M. Erb
发明人： Darrell M. Erb
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/92 , H01L27/02 , H01L29/78
CPC分类号： H01L27/1085 , H01L27/10805
摘要： The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region. One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant. Another way of achieving the desired diffusion of first polarity dopant with respect to the second polarity dopant is to select the two dopants with diffusivities approximately equal and to diffuse the first polarity dopant before the second polarity dopants is implanted into the semiconductor substrate.
摘要翻译：本发明提供一种在动态RAM中用于存储单元的半导体衬底中的电荷存储区域的制造方法，包括在衬底上形成绝缘层，在绝缘层上形成掩模层，形成至少一个孔掩模层，限定半导体衬底中的电荷存储区域的孔，通过孔径注入第一极性的掺杂离子以通过衬底扩散，以及通过孔径注入第二极性的掺杂剂离子，以通过衬底扩散到比第一极性掺杂剂扩散程度小，使得第一极性掺杂剂相对于第二极性掺杂剂的扩散的扩散形成基本上与掩模层孔的边缘对准的PN结，以限定电荷存储区域的周边。将第二极性掺杂剂扩散到比衬底中的第一极性掺杂剂更小程度的一种方法是选择具有大于第二极性掺杂剂的扩散率的第一极性掺杂剂。实现第一极性掺杂剂相对于第二极性掺杂剂的期望扩散的另一种方法是选择具有大致相等的扩散率的两种掺杂剂，并且在将第二极性掺杂剂注入到半导体衬底之前扩散第一极性掺杂剂。

10. 发明授权

US06869878B1 Method of forming a selective barrier layer using a sacrificial layer 失效
标题翻译：使用牺牲层形成选择性阻挡层的方法
公开(公告)号：US06869878B1
公开(公告)日：2005-03-22
申请号：US10367406
申请日：2003-02-14
申请人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
发明人： Ercan Adem , John E. Sanchez , Darrell M. Erb , Suzette K. Pangrle
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76885
摘要： The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.
摘要翻译：通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法，增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和性能。该方法包括在衬底上形成牺牲介电层。在牺牲电介质层中形成金属化图案。阻挡层选择性地沉积在金属化图案上。通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分，从而防止相邻金属化特征由阻挡层部分桥接。然后形成层间电介质层代替牺牲电介质层。与常规的覆盖层沉积的氮化硅阻挡层相比，选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。

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