会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Selective electroplating with direct contact chemical polishing
    • 选择性电镀与直接接触化学抛光
    • US06454916B1
    • 2002-09-24
    • US09477810
    • 2000-01-05
    • Fei WangSteven C. AvanzinoDarrell M. Erb
    • Fei WangSteven C. AvanzinoDarrell M. Erb
    • C25D1700
    • C25D5/22B23H5/08C25D7/12C25D17/001
    • A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.
    • 沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。 扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。 电镀材料填充图案化到半导体晶片的衬底中的凹槽,但是由于扩散器的接触和旋转,防止了在半导体晶片的顶表面上形成很大程度。 由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上,所以化学机械抛光(CMP)平面化被显着地减少或完全消除。
    • 5. 发明授权
    • Low temperature dielectric deposition to improve copper electromigration performance
    • 低温介电沉积提高铜电迁移性能
    • US06756306B2
    • 2004-06-29
    • US10334387
    • 2002-12-30
    • Steven C. AvanzinoDarrell M. Erb
    • Steven C. AvanzinoDarrell M. Erb
    • H01L2144
    • H01L21/02118H01L21/02167H01L21/02271H01L21/312H01L21/314H01L21/76801H01L21/76829H01L21/76834
    • The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.
    • 通过用于在金属化图案上沉积钝化层的化学气相沉积工艺来增强镶嵌在介电材料层的表面中的平坦化金属化特征(例如铜)的可靠性和电迁移寿命,其包括保持在上部 处于或低于第一温度的金属化特征的表面是预先沉积在其上的抑制膜。 抑制膜基本上抑制在第一温度以下的金属化特征的表面上形成氧化物层。 钝化层沉积在高于第一温度的第二温度下发生,使得去除抑制膜和钝化层的形成之间的时间间隔足够短,从而基本上抑制金属特征表面上的氧化物的形成。
    • 6. 发明授权
    • Anneal hillock suppression method in integrated circuit interconnects
    • 集成电路互连中的退火小丘抑制方法
    • US06500754B1
    • 2002-12-31
    • US09999661
    • 2001-10-31
    • Darrell M. ErbSteven C. AvanzinoAlline F. Myers
    • Darrell M. ErbSteven C. AvanzinoAlline F. Myers
    • H01L214763
    • H01L21/76883
    • An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.
    • 因此,提供了具有半导体器件的半导体衬底的集成电路和制造方法。 在半导体基板上形成器件电介质层,在器件电介质层上形成的沟道电介质层形成有开口部。 阻挡层对通道开口进行排列,并且导体芯填充阻挡层上的开口。 在导体芯和阻挡层平坦化之前,在400℃及以上的高温下进行半导体衬底的退火以刺激晶粒生长。 在平坦化之后,随后的钝化层或覆盖层的高温沉积将不会导致晶粒生长并且抑制小丘。
    • 9. 发明授权
    • High capacity semiconductor capacitance device structure
    • 大容量半导体电容器件结构
    • US4745454A
    • 1988-05-17
    • US926600
    • 1986-11-03
    • Darrell M. Erb
    • Darrell M. Erb
    • H01L21/8242H01L27/108H01L29/92H01L27/02H01L29/78
    • H01L27/1085H01L27/10805
    • The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region. One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant. Another way of achieving the desired diffusion of first polarity dopant with respect to the second polarity dopant is to select the two dopants with diffusivities approximately equal and to diffuse the first polarity dopant before the second polarity dopants is implanted into the semiconductor substrate.
    • 本发明提供一种在动态RAM中用于存储单元的半导体衬底中的电荷存储区域的制造方法,包括在衬底上形成绝缘层,在绝缘层上形成掩模层,形成至少一个孔 掩模层,限定半导体衬底中的电荷存储区域的孔,通过孔径注入第一极性的掺杂离子以通过衬底扩散,以及通过孔径注入第二极性的掺杂剂离子,以通过衬底扩散到 比第一极性掺杂剂扩散程度小,使得第一极性掺杂剂相对于第二极性掺杂剂的扩散的扩散形成基本上与掩模层孔的边缘对准的PN结,以限定电荷存储区域的周边 。 将第二极性掺杂剂扩散到比衬底中的第一极性掺杂剂更小程度的一种方法是选择具有大于第二极性掺杂剂的扩散率的第一极性掺杂剂。 实现第一极性掺杂剂相对于第二极性掺杂剂的期望扩散的另一种方法是选择具有大致相等的扩散率的两种掺杂剂,并且在将第二极性掺杂剂注入到半导体衬底之前扩散第一极性掺杂剂。
    • 10. 发明授权
    • Method of forming a selective barrier layer using a sacrificial layer
    • 使用牺牲层形成选择性阻挡层的方法
    • US06869878B1
    • 2005-03-22
    • US10367406
    • 2003-02-14
    • Ercan AdemJohn E. SanchezDarrell M. ErbSuzette K. Pangrle
    • Ercan AdemJohn E. SanchezDarrell M. ErbSuzette K. Pangrle
    • H01L21/44H01L21/4763H01L21/768
    • H01L21/76849H01L21/76807H01L21/76885
    • The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.
    • 通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法,增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件(例如铜)中的平面化金属化图案的可靠性和性能。 该方法包括在衬底上形成牺牲介电层。 在牺牲电介质层中形成金属化图案。 阻挡层选择性地沉积在金属化图案上。 通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分,从而防止相邻金属化特征由阻挡层部分桥接。 然后形成层间电介质层代替牺牲电介质层。 与常规的覆盖层沉积的氮化硅阻挡层相比,选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。