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1. 发明授权

US06511884B1 Method to form and/or isolate vertical transistors 有权
标题翻译：形成和/或隔离垂直晶体管的方法
公开(公告)号：US06511884B1
公开(公告)日：2003-01-28
申请号：US09972503
申请日：2001-10-09
申请人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
发明人： Elgin Quek , Ravi Sundaresan , Yang Pan , Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.
摘要翻译：一种制造隔离垂直晶体管的方法，包括以下步骤。提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。该晶片还包括在中心晶体管区域两侧的STI区域。将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。具有侧壁的立柱。在晶片上形成衬垫介质层，衬在垂直柱上。在焊盘介电层上形成氮化物层。该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。图案化的氮化物和焊盘介电层被去除。去除图案化的硬掩模。栅极氧化物生长在晶片和垂直柱的暴露部分上。在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的垂直晶体管。

2. 发明授权

US06372569B1 Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance 有权
标题翻译：选择性形成富氢PECVD氮化硅，以改善NMOS晶体管性能
公开(公告)号：US06372569B1
公开(公告)日：2002-04-16
申请号：US09483035
申请日：2000-01-18
申请人： Yong Meng Lee , Gao Feng , Yunqzang Zhang , Ravi Sundaresan
发明人： Yong Meng Lee , Gao Feng , Yunqzang Zhang , Ravi Sundaresan
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.
摘要翻译：一种在半导体器件中选择性地形成SiN层的方法，包括以下步骤。提供具有形成在其中的至少一个PMOS晶体管和一个NMOS晶体管的半导体结构。 PMOS和NMOS晶体管各自具有源极/漏极区域，栅极和自对准硅化物接触区域。在半导体结构和PMOS和NMOS晶体管上沉积未掺杂的硅酸盐玻璃（USG）层。富含H 2 O的PECVD氮化硅层沉积在未掺杂的硅酸盐玻璃层上并在PMOS和NMOS晶体管之上。从富于PMOS晶体管的图案化，蚀刻和去除富H2的PECVD氮化硅层。在该结构上形成层间电介质（ILD）层。 ILD层被致密化，由此氢从NMOS晶体管上的富H 2 PECVD氮化硅层扩散到NMOS晶体管的源极/漏极。

3. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

4. 发明申请

US20090042359A1 Structure and Method of Producing Isolation with Non-Dopant Implantation 有权
标题翻译：用非掺杂植入法分离生产的结构和方法
公开(公告)号：US20090042359A1
公开(公告)日：2009-02-12
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/71 , H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

5. 发明申请

US20080224228A1 CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE 有权
标题翻译：电容器顶板通过源/排出形成1T存储器件
公开(公告)号：US20080224228A1
公开(公告)日：2008-09-18
申请号：US11686475
申请日：2007-03-15
申请人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
发明人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/1085 , H01L27/11
摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
摘要翻译：用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。示例设备包括以下。形成为围绕衬底上的有源区域的隔离膜。形成在有源区域的一部分上的栅极电介质和栅电极。与栅电极相邻的衬底中的源极元件和漏极元件。漏极元件由漏区和底板区组成。漏极区域位于底板区域和栅极结构之间。电容器电介质和电容器顶板在底板区域的至少部分上方。

6. 发明授权

US07393746B2 Post-silicide spacer removal 失效
标题翻译：后硅化物间隔物去除
公开(公告)号：US07393746B2
公开(公告)日：2008-07-01
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
IPC分类号： H01L21/33
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
摘要翻译：一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。然后，该方法在衬底的暴露区域的表面上形成硅化物。该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

7. 发明申请

US20080026523A1 Structure and method to implement dual stressor layers with improved silicide control 审中-公开
标题翻译：具有改进的硅化物控制的双应力层的结构和方法
公开(公告)号：US20080026523A1
公开(公告)日：2008-01-31
申请号：US11495508
申请日：2006-07-28
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.
摘要翻译：用于制造半导体器件的方法的示例实施例包括以下。我们提供具有第一器件区域和第二器件区域的衬底。我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。第一应力层在第一器件区域中的衬底上施加第一类应力。我们在第二设备区域上形成第二应力层。第二应力层在第二器件区域中的衬底上施加第二类应力。另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。

8. 发明申请

US20070281410A1 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US20070281410A1
公开(公告)日：2007-12-06
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

9. 发明授权

US06787404B1 Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance 有权
标题翻译：形成具有降低的栅 - 源 - 重叠电容的双栅绝缘体（SOI）晶体管的方法
公开(公告)号：US06787404B1
公开(公告)日：2004-09-07
申请号：US10664262
申请日：2003-09-17
申请人： Yong Meng Lee , Da Jin , David Vigar
发明人： Yong Meng Lee , Da Jin , David Vigar
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66553 , H01L29/78648
摘要： A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer. A conformal oxide layer is formed around the channel portion of the patterned SOI silicon layer. A gate is formed within the patterned dummy layer opening. The gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer. The patterned dummy layer is then removed to form the double-gated transistor.
摘要翻译：一种形成双门控晶体管的方法，包括以下顺序步骤。提供了具有形成在其上的SOI结构的衬底。 SOI结构包括下部SOI氧化物层和上部SOI硅层。图案化SOI硅层以形成图案化SOI硅层，其包括通过沟道部分连接的源极区域和漏极区域。在图案化SOI硅层上形成包围氧化物层，以形成被封装的图案化SOI硅层。在封装的图案化SOI硅层上形成图案化虚拟层。具有开口的图案化虚拟层具有暴露的侧壁，暴露：被封装的图案化SOI硅层的沟道部分; 以及SOI氧化物层的上表面的部分。偏移间隔物在图案化虚拟层开口的暴露的侧壁上方。蚀刻SOI氧化物层，同时最小化SOI氧化物层的上表面的底切部分被切入SOI氧化物层中以形成最小的底切。最小化底切工艺也去除了图案化SOI硅层的通道部分上的偏移间隔物和包围氧化物层。在图案化SOI硅层的沟道部分周围形成保形氧化物层。在图案化虚拟层开口内形成栅极。栅极包括在图案化SOI硅层上方的上栅极和在图案化SOI硅层下方的下栅极。然后去除图案化的虚拟层以形成双门控晶体管。

10. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

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