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1. 发明授权

US07393746B2 Post-silicide spacer removal 失效
标题翻译：后硅化物间隔物去除
公开(公告)号：US07393746B2
公开(公告)日：2008-07-01
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
IPC分类号： H01L21/33
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
摘要翻译：一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。然后，该方法在衬底的暴露区域的表面上形成硅化物。该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

2. 发明申请

US20080090370A1 Post-silicide spacer removal 失效
公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

3. 发明授权

US07598572B2 Silicided polysilicon spacer for enhanced contact area 失效
标题翻译：用于增强接触面积的硅化多晶硅间隔物
公开(公告)号：US07598572B2
公开(公告)日：2009-10-06
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L29/40
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

4. 发明申请

US20080102612A1 SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA 失效
标题翻译：用于增强接触面积的多孔聚硅氧烷绝缘子
公开(公告)号：US20080102612A1
公开(公告)日：2008-05-01
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L21/44 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

5. 发明授权

US07977185B2 Method and apparatus for post silicide spacer removal 有权
标题翻译：后硅化物间隔物去除的方法和装置
公开(公告)号：US07977185B2
公开(公告)日：2011-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/33
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

6. 发明申请

US20070161244A1 METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL 有权
标题翻译：硅胶分离器去除后的方法和装置
公开(公告)号：US20070161244A1
公开(公告)日：2007-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

7. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

8. 发明申请

US20090042359A1 Structure and Method of Producing Isolation with Non-Dopant Implantation 有权
标题翻译：用非掺杂植入法分离生产的结构和方法
公开(公告)号：US20090042359A1
公开(公告)日：2009-02-12
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/71 , H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

9. 发明申请

US20080224228A1 CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE 有权
标题翻译：电容器顶板通过源/排出形成1T存储器件
公开(公告)号：US20080224228A1
公开(公告)日：2008-09-18
申请号：US11686475
申请日：2007-03-15
申请人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
发明人： Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Shailendra Mishra , Johnny Widodo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/1085 , H01L27/11
摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
摘要翻译：用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。示例设备包括以下。形成为围绕衬底上的有源区域的隔离膜。形成在有源区域的一部分上的栅极电介质和栅电极。与栅电极相邻的衬底中的源极元件和漏极元件。漏极元件由漏区和底板区组成。漏极区域位于底板区域和栅极结构之间。电容器电介质和电容器顶板在底板区域的至少部分上方。

10. 发明申请

US20080026523A1 Structure and method to implement dual stressor layers with improved silicide control 审中-公开
标题翻译：具有改进的硅化物控制的双应力层的结构和方法
公开(公告)号：US20080026523A1
公开(公告)日：2008-01-31
申请号：US11495508
申请日：2006-07-28
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.
摘要翻译：用于制造半导体器件的方法的示例实施例包括以下。我们提供具有第一器件区域和第二器件区域的衬底。我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。第一应力层在第一器件区域中的衬底上施加第一类应力。我们在第二设备区域上形成第二应力层。第二应力层在第二器件区域中的衬底上施加第二类应力。另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。

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