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1. 发明授权

US07999325B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US07999325B2
公开(公告)日：2011-08-16
申请号：US12241073
申请日：2008-09-30
申请人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
发明人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

2. 发明申请

US20090026549A1 METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS 有权
标题翻译：灭火后取出间隔物的方法，以增强接触件在MOS上的阻塞衬里应力
公开(公告)号：US20090026549A1
公开(公告)日：2009-01-29
申请号：US12241073
申请日：2008-09-30
申请人： Young Way TEH , Yong Meng LEE , Chung Woh LAI , Wenhe LIN , Khee Yong LIM , Wee Leng TAN , John SUDIJONO , Hui Peng KOH , Liang Choo HSIA
发明人： Young Way TEH , Yong Meng LEE , Chung Woh LAI , Wenhe LIN , Khee Yong LIM , Wee Leng TAN , John SUDIJONO , Hui Peng KOH , Liang Choo HSIA
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

3. 发明申请

US20070281410A1 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US20070281410A1
公开(公告)日：2007-12-06
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

4. 发明授权

US06339021B1 Methods for effective nickel silicide formation 有权
标题翻译：有效的硅化镍形成方法
公开(公告)号：US06339021B1
公开(公告)日：2002-01-15
申请号：US09850992
申请日：2001-05-09
申请人： Wee Leng Tan , Kin Leong Pey , Simon Chooi
发明人： Wee Leng Tan , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： Methods for forming a high quality nickel silicide film in the fabrication of an integrated circuit are described. A semiconductor substrate is provided having silicon regions to be silicided wherein a native oxide layer forms on the silicon regions. A nickel layer is deposited overlying the silicon regions to be silicided. A titanium layer is deposited overlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium layer diffuse through the nickel layer and react with the native oxide layer and whereby the nickel is transformed to nickel silicide where it overlies the silicon regions and wherein the nickel not overlying the silicon regions is unreacted. In an alternative method, a titanium nitride layer over the titanium layer traps atmospheric oxygen freeing all of the titanium in the titanium layer to react with the underlying native oxide. The unreacted nickel layer is removed to complete formation of a nickel silicide film in the manufacture of an integrated circuit. In another method, a monolayer of titanium is deposited by atomic layer chemical vapor deposition underlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium monolayer react with the native oxide layer and whereby the the nickel is transformed to nickel silicide.
摘要翻译：描述了在制造集成电路中形成高质量硅化镍膜的方法。提供了具有要被硅化的硅区域的半导体衬底，其中在硅区域上形成自然氧化物层。沉积在要被硅化的硅区域上的镍层。沉积在镍层上的钛层。退火基板，由此来自钛层的钛原子通过镍层扩散并与天然氧化物层反应，由此将镍转化为硅化镍，其中它覆盖在硅区域上，并且其中未覆盖硅区域的镍是未反应的。在另一种方法中，钛层上方的氮化钛层捕获大气氧，释放钛层中的所有钛以与下面的天然氧化物反应。去除未反应的镍层以在集成电路的制造中完成硅化镍膜的形成。在另一种方法中，通过镍层下面的原子层化学气相沉积沉积单层的钛。退火基板，由此钛单层的钛原子与天然氧化物层反应，由此将镍转化为硅化镍。

5. 发明授权

US08624329B2 Spacer-less low-K dielectric processes 有权
标题翻译：无隔离低K介电工艺
公开(公告)号：US08624329B2
公开(公告)日：2014-01-07
申请号：US12613541
申请日：2009-11-06
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

6. 发明申请

US20100059831A1 Spacer-less Low-K Dielectric Processes 有权
标题翻译：无隔离低K介电工艺
公开(公告)号：US20100059831A1
公开(公告)日：2010-03-11
申请号：US12613541
申请日：2009-11-06
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L27/088 , H01L29/78 , H01L21/31 , H01L21/306
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

7. 发明授权

US07445978B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US07445978B2
公开(公告)日：2008-11-04
申请号：US11122666
申请日：2005-05-04
申请人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
发明人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，栅极，源极和漏极区域在形成应力产生层之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

8. 发明授权

US07615427B2 Spacer-less low-k dielectric processes 有权
标题翻译：无隔离低k介电过程
公开(公告)号：US07615427B2
公开(公告)日：2009-11-10
申请号：US11447565
申请日：2006-06-05
申请人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
发明人： Yong Meng Lee , Young Way Teh , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
摘要翻译：第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。这用于减小寄生电容。此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。示例性实施例可以提高设备性能，例如边缘振荡器的性能。

9. 发明申请

US20080315317A1 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS 审中-公开
标题翻译：具有补充应变通道的半导体系统
公开(公告)号：US20080315317A1
公开(公告)日：2008-12-25
申请号：US11767449
申请日：2007-06-22
申请人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
发明人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/7843
摘要： A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
摘要翻译：提供一种半导体系统，包括提供半导体衬底; 在半导体衬底中形成PMOS和NMOS晶体管; 在半导体衬底上形成拉伸应变层; 并放宽PMOS晶体管周围的拉伸应变层。

10. 发明授权

US07256084B2 Composite stress spacer 有权
标题翻译：复合应力间隔
公开(公告)号：US07256084B2
公开(公告)日：2007-08-14
申请号：US11122667
申请日：2005-05-04
申请人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
发明人： Khee Yong Lim , Wenhe Lin , Chung Woh Lai , Yong Meng Lee , Liang Choo Hsia , Young Way Teh , John Sudijono , Wee Leng Tan , Hui Peng Koh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
摘要翻译：示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。这提高了设备性能。

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