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1. 发明申请

US20080026523A1 Structure and method to implement dual stressor layers with improved silicide control 审中-公开
标题翻译：具有改进的硅化物控制的双应力层的结构和方法
公开(公告)号：US20080026523A1
公开(公告)日：2008-01-31
申请号：US11495508
申请日：2006-07-28
申请人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
发明人： Yong Meng Lee , Haining S. Yang , Victor Chan , Eng Hua Lim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.
摘要翻译：用于制造半导体器件的方法的示例实施例包括以下。我们提供具有第一器件区域和第二器件区域的衬底。我们在第一器件区域提供第一类型FET晶体管，并在第二器件区域中提供第二类型FET晶体管。我们在第一和第二器件区域上形成蚀刻停止层，并在第一器件区域上形成第一应激源层。第一应力层在第一器件区域中的衬底上施加第一类应力。我们在第二设备区域上形成第二应力层。第二应力层在第二器件区域中的衬底上施加第二类应力。另一示例性实施例是具有蚀刻停止层的双应力层器件的结构。

2. 发明授权

US07545004B2 Method and structure for forming strained devices 失效
标题翻译：形成应变装置的方法和结构
公开(公告)号：US07545004B2
公开(公告)日：2009-06-09
申请号：US10907689
申请日：2005-04-12
申请人： Haining S. Yang , Eng Hua Lim
发明人： Haining S. Yang , Eng Hua Lim
IPC分类号： H01L29/78 , H01L29/34
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823871
摘要： A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.
摘要翻译：一种用于制造器件的方法包括：基于沉积的第一层和第二层的垂直边缘，对掩模层的极限垂直边界条件进行映射。基于映射步骤，掩模层沉积在第二层的部分上。蚀刻第二层的暴露区域以在第一层和第二层之间形成平滑的边界。剥离抗蚀剂层。所得到的器件是改进的PFET器件和NFET器件，其在第一和第二层之间具有平滑的边界，使得可以在光滑边界处形成接触，而不会过度蚀刻器件的其它区域。

3. 发明授权

US08148221B2 Double anneal with improved reliability for dual contact etch stop liner scheme 有权
标题翻译：双重退火，具有改进的双接触蚀刻停止衬垫方案的可靠性
公开(公告)号：US08148221B2
公开(公告)日：2012-04-03
申请号：US12581207
申请日：2009-10-19
申请人： Khee Yong Lim , Victor Chan , Eng Hua Lim , Wenhe Lin , Jamin F. Fen
发明人： Khee Yong Lim , Victor Chan , Eng Hua Lim , Wenhe Lin , Jamin F. Fen
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/3003 , H01L21/76802 , H01L21/76829 , H01L21/76834 , H01L21/76843 , H01L21/76895 , H01L21/823864 , H01L29/7843
摘要： A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
摘要翻译：使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。然后我们进行第一次氘退火。我们在PFET区域上形成PFET压电蚀刻停止衬垫。我们在衬底上形成具有接触开口的（ILD）电介质层。我们进行第二次氘退火。第二次氘退火的温度小于第一次氘退火的温度。

4. 发明授权

US07615433B2 Double anneal with improved reliability for dual contact etch stop liner scheme 有权
标题翻译：双重退火，具有改进的双接触蚀刻停止衬垫方案的可靠性
公开(公告)号：US07615433B2
公开(公告)日：2009-11-10
申请号：US11304455
申请日：2005-12-15
申请人： Khee Yong Lim , Victor Chan , Eng Hua Lim , Wenhe Lin , Jamin F. Fen
发明人： Khee Yong Lim , Victor Chan , Eng Hua Lim , Wenhe Lin , Jamin F. Fen
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/3003 , H01L21/76802 , H01L21/76829 , H01L21/76834 , H01L21/76843 , H01L21/76895 , H01L21/823864 , H01L29/7843
摘要： A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
摘要翻译：使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。然后我们进行第一次氘退火。我们在PFET区域上形成PFET压电蚀刻停止衬垫。我们在衬底上形成具有接触开口的（ILD）电介质层。我们进行第二次氘退火。第二次氘退火的温度小于第一次氘退火的温度。

5. 发明授权

US06664153B2 Method to fabricate a single gate with dual work-functions 失效
标题翻译：制造具有双功能功能的单门的方法
公开(公告)号：US06664153B2
公开(公告)日：2003-12-16
申请号：US10072099
申请日：2002-02-08
申请人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L21336
CPC分类号： H01L29/4983 , H01L21/28035
摘要： A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.
摘要翻译：描述了一种形成具有双功能功能的单门的方法。在基板上形成覆盖栅介质层的栅电极。栅电极的侧壁被选择性掺杂，由此掺杂侧壁具有第一功函数，并且由此未掺杂的栅电极的中心部分具有第二功函数，以在制造中完成形成具有多个功函数的单个栅极的集成电路。

6. 发明授权

US06429109B1 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate 有权
标题翻译：通过在氧化物和栅极之间使用牺牲金属来形成高k电介质和硅化物以减少多余的方法
公开(公告)号：US06429109B1
公开(公告)日：2002-08-06
申请号：US10017953
申请日：2001-12-14
申请人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
发明人： Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen , Chew Hoe Ang , Eng Hua Lim , Randall Cha
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28176 , H01L21/28238 , H01L29/513 , H01L29/517
摘要： A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
摘要翻译：一种形成浇口的方法，包括以下步骤。提供基板。在衬底上形成预栅极结构。预栅结构包括在上栅极导体层和下栅极介电层之间的牺牲金属层。预栅结构退火形成栅极。该栅极包括：由牺牲金属层的一部分形成的上硅化物层和来自退火的上部栅极导体层的一部分; 以及由栅极电介质层的一部分和来自退火的牺牲金属层的一部分形成的下部金属氧化物层。

7. 发明授权

US06350661B2 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06350661B2
公开(公告)日：2002-02-26
申请号：US09882682
申请日：2001-06-18
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

8. 发明授权

US5956137A In-line process monitoring using micro-raman spectroscopy 失效
标题翻译：使用微拉曼光谱的在线过程监控
公开(公告)号：US5956137A
公开(公告)日：1999-09-21
申请号：US186389
申请日：1998-11-05
申请人： Eng Hua Lim , Kin-Leong Pey , Harianto Wong , Kong Hean Lee
发明人： Eng Hua Lim , Kin-Leong Pey , Harianto Wong , Kong Hean Lee
IPC分类号： G01J3/44 , H01L21/00
CPC分类号： G01J3/44
摘要： An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.
摘要翻译：描述了用于识别诸如细线图案的微结构中的相位的在线非破坏性方法。这是通过观察微结构的拉曼光谱来实现的。特别的应用是使用SALICIDE工艺制备的硅化物层，其中快速热退火之前和之后的晶相通常是不同的。这反映在拉曼光谱中不同线的出现，从而可以确定每相的分数。如果在退火期间硅化物层凝聚，则这也由拉曼光谱检测。该方法已被成功地应用到约0.35微米的线宽。

9. 发明授权

US06664156B1 Method for forming L-shaped spacers with precise width control 有权
标题翻译：用于形成具有精确宽度控制的L形间隔件的方法
公开(公告)号：US06664156B1
公开(公告)日：2003-12-16
申请号：US10209573
申请日：2002-07-31
申请人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
发明人： Chew Hoe Ang , Eng Hua Lim , Wenhe Lin , Jia Zhen Zheng
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.
摘要翻译：一种在半导体器件中制造L形间隔物的方法。栅极结构设置在衬底上。我们在栅极电介质层和衬底上形成第一电介质层。接下来，在第一电介质层上形成第二电介质层。然后，在第二电介质层上形成第三电介质层。第三介电层被各向异性蚀刻以在第二介电层上形成一次性间隔物。使用一次性间隔件作为掩模对第二介电层和第一介电层进行各向异性蚀刻，以形成顶部和底部的L形间隔件。去除一次性间隔物。在优选实施例中，第一，第二和第三电介质层通过原子层沉积（ALD）或ALCVD工艺形成。

10. 发明授权

US06632745B1 Method of forming almost L-shaped spacer for improved ILD gap fill 有权
标题翻译：形成几乎L型间隔物以改善ILD间隙填充的方法
公开(公告)号：US06632745B1
公开(公告)日：2003-10-14
申请号：US10222387
申请日：2002-08-16
申请人： Chiew Wah Yap , Zheng Zou , Eng Hua Lim , Nguyen Lac , Yelehanka Pradeep , Manni Lal
发明人： Chiew Wah Yap , Zheng Zou , Eng Hua Lim , Nguyen Lac , Yelehanka Pradeep , Manni Lal
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/665
摘要： A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created. Under the first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited, The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched. Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.
摘要翻译：在衬底的有源表面上形成图案化和蚀刻的栅极材料层，形成衬垫氧化物层，形成栅极间隔物。在本发明的第一个实施方案中，存在一层TEOS 在其上沉积氮化物层的所产生的结构上。蚀刻氮化物层，该蚀刻扩展到通过TEOS层产生开口的过蚀刻，其中该层覆盖在栅极间隔物上。然后进一步蚀刻栅极间隔物。在本发明的第二实施例中，在所创建的结构上沉积TEOS层。蚀刻TEOS层，停留在栅极间隔物的氮化硅上。然后进一步蚀刻栅极间隔物

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