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1. 发明授权

US5475690A Delay compensated signal propagation 失效
标题翻译：延迟补偿信号传播
公开(公告)号：US5475690A
公开(公告)日：1995-12-12
申请号：US337352
申请日：1994-11-10
申请人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
发明人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
IPC分类号： G06F13/42 , H04J3/06
CPC分类号： G06F13/4239
摘要： In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.
摘要翻译：在计算机系统中，数字信号从输出寄存器发送，沿着第一信令路径传播并由输入寄存器接收。信令路径包括地址缓冲器，高速缓冲存储器，主存储器和互连网络。数字信号经历的固有延迟的影响被测量为相对于通过复制第一信令路径的延迟的第二信令路径传播的参考时钟信号的延迟值。延迟值用于选择性地延迟数字信号以保持发送和接收的数字信号之间的固定关系。延迟测量和调节通过驱动参考和数字信号通过类似的抽头延迟线，即延迟线的输出抽头控制延迟线的输出抽头来提供。提供存储锁存器以将测量的延迟值保持在连续采样之间。

2. 发明授权

US06360285B1 Apparatus for determining memory bank availability in a computer system 失效
标题翻译：用于确定计算机系统中的存储体可用性的装置
公开(公告)号：US06360285B1
公开(公告)日：2002-03-19
申请号：US08269234
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
发明人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
IPC分类号： G06F1202
CPC分类号： G06F13/16
摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.
摘要翻译：根据本发明，一种装置包括具有存储体可用信号的系统总线。耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制。通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

3. 发明授权

US6076129A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US6076129A
公开(公告)日：2000-06-13
申请号：US869610
申请日：1997-06-06
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

4. 发明授权

US5666551A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US5666551A
公开(公告)日：1997-09-09
申请号：US590802
申请日：1996-01-24
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。用于跟踪在总线上发生的地址和命令事务的机制针对地址总线上发生的每个地址和命令事务产生相应的序列号标签。由数据总线排序器存储与节点发起数据事务的地址和命令事务对应的那些序列号标签。数据总线序列器还包括用于对在数据总线上发生的数据事务的数量进行计数的电路，将计数的数据事务数与存储的序列号标签进行比较，并响应于该比较在数据总线上启动数据事务。

5. 发明授权

US5430888A Pipeline utilizing an integral cache for transferring data to and from a register 失效
标题翻译：管道利用集成缓存将数据传送到寄存器和从寄存器传输数据
公开(公告)号：US5430888A
公开(公告)日：1995-07-04
申请号：US143509
申请日：1993-10-26
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
摘要翻译：用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。流水线包括支持多个未完成读请求未命中的缓冲区。来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。然后可以用所请求的数据填充高速缓存存储器。在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

6. 发明授权

US5148536A Pipeline having an integral cache which processes cache misses and loads data in parallel 失效
标题翻译：具有整合速度的流水线，并行处理缓存和负载数据
公开(公告)号：US5148536A
公开(公告)日：1992-09-15
申请号：US224483
申请日：1988-07-25
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

7. 发明授权

US6122714A Order supporting mechanisms for use in a switch-based multi-processor system 失效
标题翻译：用于基于交换机的多处理器系统中的订单支持机制
公开(公告)号：US6122714A
公开(公告)日：2000-09-19
申请号：US957298
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
IPC分类号： G06F12/08 , G06F9/46 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

8. 发明授权

US5179674A Method and apparatus for predicting valid performance of virtual-address to physical-address translations 失效
标题翻译：用于预测虚拟地址到物理地址转换的有效性能的方法和装置
公开(公告)号：US5179674A
公开(公告)日：1993-01-12
申请号：US224443
申请日：1988-07-25
申请人： Douglas D. Williams , David M. Fenwick , Timothy J. Stanley
发明人： Douglas D. Williams , David M. Fenwick , Timothy J. Stanley
IPC分类号： G06F12/08 , G06F12/10 , G06F17/16
CPC分类号： G06F12/10 , G06F2212/655
摘要： A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

9. 发明授权

US5175613A Package for EMI, ESD, thermal, and mechanical shock protection of circuit chips 失效
标题翻译：用于电路芯片的EMI，ESD，热和机械冲击保护的封装
公开(公告)号：US5175613A
公开(公告)日：1992-12-29
申请号：US644401
申请日：1991-01-18
申请人： Charles R. Barker, III , Richard J. Casabona , David M. Fenwick
发明人： Charles R. Barker, III , Richard J. Casabona , David M. Fenwick
IPC分类号： H01L23/00 , H01L23/32 , H01L23/367 , H01L23/552 , H01L23/60
CPC分类号： H01L23/562 , H01L23/32 , H01L23/3675 , H01L23/552 , H01L23/60 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/16152 , H01L2924/16251 , H01L2924/3025
摘要： A package for integrated circuit chips, or other electrical devices, provides mechanical shock and thermal protection for the chips, and in addition, protects the chips from electromagnetic interference and electrostatic discharge. The package includes a printed wiring board base for reception of one or more circuit chips, and a conductive heat sink and cover. The conductive heat sink, in conjunction with a reference plane in the wiring board base, acts as an EMI shield for the chips. The heat sink is covered with an insulating layer, on top of which, a conductive coating is placed. The conductive coating is electrically connected to the reference plane, and the two act to protect the chips from electrostatic discharges. Compliant pads support the chips, and a thermally conductive elastomer can be placed on top of each chip between the chips and the inner top surface of the heat sink. The chips are thereby held securely in position, and are thermally connected to the heat sink.
摘要翻译：用于集成电路芯片或其他电气设备的封装为芯片提供机械冲击和热保护，此外，保护芯片免受电磁干扰和静电放电。该封装包括用于接收一个或多个电路芯片的印刷线路板基座和导电散热器和盖。导电散热器与布线板底座中的参考平面结合，用作芯片的EMI屏蔽。散热器被绝缘层覆盖，其上放置导电涂层。导电涂层电连接到参考平面，两者用于保护芯片免受静电放电。兼容焊盘支持芯片，并且导热弹性体可以放置在芯片和散热器的内顶表面之间的每个芯片的顶部。因此，芯片牢固地保持在适当位置，并且热连接到散热器。

10. 发明授权

US06256694B1 Distributed early arbitration 失效
标题翻译：分散的早期仲裁
公开(公告)号：US06256694B1
公开(公告)日：2001-07-03
申请号：US08269251
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F1336
CPC分类号： G06F13/36 , G06F12/0884 , G06F13/368
摘要： A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.
摘要翻译：一个指挥官模块，其耦合到包括系统总线控制请求信号并与系统总线控制请求信号之一相关联的系统总线，包括用于确定是否需要控制系统总线的装置，以及用于请求控制系统总线的装置以通过断言相关的系统总线控制请求信号来确定是否需要这样的控制。包括系统总线和耦合到系统总线的至少两个这样的指挥器模块的计算机系统以及用于仲裁以控制系统总线的装置，其中仲裁装置耦合到并且响应于系统总线控制请求信号。

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