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1. 发明授权

US5475690A Delay compensated signal propagation 失效
标题翻译：延迟补偿信号传播
公开(公告)号：US5475690A
公开(公告)日：1995-12-12
申请号：US337352
申请日：1994-11-10
申请人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
发明人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
IPC分类号： G06F13/42 , H04J3/06
CPC分类号： G06F13/4239
摘要： In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.
摘要翻译：在计算机系统中，数字信号从输出寄存器发送，沿着第一信令路径传播并由输入寄存器接收。信令路径包括地址缓冲器，高速缓冲存储器，主存储器和互连网络。数字信号经历的固有延迟的影响被测量为相对于通过复制第一信令路径的延迟的第二信令路径传播的参考时钟信号的延迟值。延迟值用于选择性地延迟数字信号以保持发送和接收的数字信号之间的固定关系。延迟测量和调节通过驱动参考和数字信号通过类似的抽头延迟线，即延迟线的输出抽头控制延迟线的输出抽头来提供。提供存储锁存器以将测量的延迟值保持在连续采样之间。

2. 发明授权

US5430888A Pipeline utilizing an integral cache for transferring data to and from a register 失效
标题翻译：管道利用集成缓存将数据传送到寄存器和从寄存器传输数据
公开(公告)号：US5430888A
公开(公告)日：1995-07-04
申请号：US143509
申请日：1993-10-26
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
摘要翻译：用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。流水线包括支持多个未完成读请求未命中的缓冲区。来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。然后可以用所请求的数据填充高速缓存存储器。在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

3. 发明授权

US5148536A Pipeline having an integral cache which processes cache misses and loads data in parallel 失效
标题翻译：具有整合速度的流水线，并行处理缓存和负载数据
公开(公告)号：US5148536A
公开(公告)日：1992-09-15
申请号：US224483
申请日：1988-07-25
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

4. 发明授权

US06754838B2 Method for reducing tuning etch in a clock-forwarded interface 失效
标题翻译：降低时钟转发接口中调谐蚀刻的方法
公开(公告)号：US06754838B2
公开(公告)日：2004-06-22
申请号：US09770589
申请日：2001-01-26
申请人： Douglas J. Burns , Roger Dame
发明人： Douglas J. Burns , Roger Dame
IPC分类号： G06F112
CPC分类号： H04L7/0008
摘要： A clock forwarding scheme for use in a system comprising a plurality of communications links, each link configured to transmit data packets and a forwarded clock from a transmitting device to a receiving device. The required delay in the forwarded clock signal is generated at the transmitting device by adding tuning etch to the signal path for the forwarded clock signal prior to transmission of the forwarded clock signal and data packets. The source device preferably has at least two clock output pins to deliver two synchronous clock signals off the device and at least two clock input pins to receive the clock signals. One of the two clock signals is delayed with respect to the other via a longer conduction path. The delayed clock signal is used to trigger logic to transmit the forwarded clock signal. The undelayed clock signal is used to trigger logic to transmit data bits.
摘要翻译：一种在包括多个通信链路的系统中使用的时钟转发方案，每个链路被配置为从发送设备向接收设备发送数据分组和转发时钟。通过在转发的时钟信号和数据分组的发送之前，通过在转发的时钟信号的信号路径上添加调谐蚀刻，在发送设备处产生所需的延迟。源装置优选地具有至少两个时钟输出引脚以从装置和至少两个时钟输入引脚输出两个同步时钟信号以接收时钟信号。两个时钟信号中的一个相对于另一个通过较长的传导路径被延迟。延迟时钟信号用于触发发送转发的时钟信号的逻辑。未延时的时钟信号用于触发发送数据位的逻辑。

5. 发明授权

US06711695B1 PECL voltage DIMM with remote multi-module etch skew compensation 失效
标题翻译： PECL电压DIMM具有远程多模块蚀刻偏移补偿
公开(公告)号：US06711695B1
公开(公告)日：2004-03-23
申请号：US09770590
申请日：2001-01-26
申请人： Douglas J. Burns , Barry S. Katz
发明人： Douglas J. Burns , Barry S. Katz
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A processor system, comprising a system board on which a processor, a memory logic controller, and a clock source are installed and a memory module on which a memory device and PLL clock driver are installed. The system board is configured to accept one or more memory modules. The clock signal generated by the clock source is distributed to the various devices on the system board by a clock buffer tree via equal length etch runs. The same clock signal is also propagated via a different length etch to the memory device on the memory module. Clock skew generated by these different clock etch lengths is removed by routing a carefully tuned feedback loop of the clock driver from the memory module to the system board and back to the clock driver on the memory module. The PLL performs a clock signal voltage translation from PECL to TTL voltage.
摘要翻译：一种处理器系统，包括其上安装有处理器，存储器逻辑控制器和时钟源的系统板以及安装有存储器件和PLL时钟驱动器的存储器模块。系统板被配置为接受一个或多个存储器模块。由时钟源产生的时钟信号通过等长蚀刻运行通过时钟缓冲器树分配到系统板上的各种器件。相同的时钟信号也通过不同长度的蚀刻传播到存储器模块上的存储器件。通过将精确调整的时钟驱动器的反馈环路从存储器模块路由到系统板并返回到存储器模块上的时钟驱动器，由这些不同的时钟蚀刻长度产生的时钟偏移被去除。 PLL执行从PECL到TTL电压的时钟信号电压转换。

6. 发明授权

US5537575A System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information 失效
标题翻译：用于处理高速缓存存储器受害者数据的系统，该缓冲存储器将数据从高速缓存传送到接口，而CPU使用高速缓存状态信息执
公开(公告)号：US5537575A
公开(公告)日：1996-07-16
申请号：US268403
申请日：1994-06-30
申请人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
发明人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus. In response to the command for transmitting cache memory victim data, the cache memory data which is waiting in the data interface, is transmitted from the data interface to main memory over the system bus.
摘要翻译：一种用于处理用于更新主存储器的高速缓存存储器受害数据的计算机系统中的方法和装置。本发明在具有通过根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块耦合到主存储器的计算机系统中操作。在执行了一个高速缓存存储器地址的READ的处理器中，对应于正在读取的高速缓存存储器地址的高速缓存存储器数据从高速缓冲存储器数据存储器发送到数据接口。高速缓存存储器数据在执行高速缓存存储器地址信息的READ期间被数据接口累积地接收。确定与高速缓存存储器地址相对应的高速缓存存储器数据是否为高速缓存存储器受害者。如果该确定确定它是缓存存储器受害者，则处理器通过系统总线发出用于将高速缓存存储器受害数据发送到主存储器的命令。响应于用于发送高速缓存存储器受害者数据的命令，在数据接口中等待的高速缓存存储器数据通过系统总线从数据接口发送到主存储器。

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