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1. 发明授权

US07395443B1 Integrated circuit with a hibernate mode and method therefor 有权
标题翻译：具有休眠模式的集成电路及其方法
公开(公告)号：US07395443B1
公开(公告)日：2008-07-01
申请号：US11023792
申请日：2004-12-28
申请人： Stephen C. Kromer , James J. Montanaro , Richard T. Witek , Kathryn J. Hoover
发明人： Stephen C. Kromer , James J. Montanaro , Richard T. Witek , Kathryn J. Hoover
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.
摘要翻译：集成电路（100）包括防火墙输入端，第一电路（110,120,170,172）和第二电路（220）。防火墙输入端子用于接收防火墙输入信号。第一电路（110,120,170,172）耦合到第一电源电压端子（203），并且具有用于提供控制信号的输出。第二电路被耦合到第二电源电压端子（210），到防火墙输入端子（214）和第一电路（110,120,170,172）。当防火墙输入信号无效时，控制信号的激活会影响第二个电路的运行。当防火墙输入信号有效时，控制信号的激活不会影响第二个电路的运行。

2. 发明授权

US5410682A In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor 失效
标题翻译：在精简指令集处理器中使用数据移位的非对齐字节写入的寄存器数据操作
公开(公告)号：US5410682A
公开(公告)日：1995-04-25
申请号：US289025
申请日：1994-08-10
申请人： Richard L. Sites , Richard T. Witek
发明人： Richard L. Sites , Richard T. Witek
IPC分类号： G06F9/30 , G06F9/308 , G06F9/312 , G06F9/38 , G06F12/04 , G06F15/76
CPC分类号： G06F12/1027 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30054 , G06F9/30072 , G06F9/30087 , G06F9/3816 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F2212/652
摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.
摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。包括允许使用先前建立的数据结构的字节操作指令包括进行寄存器中字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。提供加载/锁定和存储/条件指令允许实现原子字节写入。

3. 发明授权

US5291581A Apparatus and method for synchronization of access to main memory signal groups in a multiprocessor data processing system 失效
标题翻译：用于在多处理器数据处理系统中访问主存储器信号组的同步的装置和方法
公开(公告)号：US5291581A
公开(公告)日：1994-03-01
申请号：US844968
申请日：1992-02-28
申请人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
发明人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
IPC分类号： G06F9/46 , G06F15/78 , G06F12/14
CPC分类号： G06F9/52 , G06F15/8069
摘要： In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto. The altered data element is returned to the main memory unit location and the main memory interlock signal is released, thereby completing the instruction.
摘要翻译：在多处理器数据处理单元中，具有系统广泛意义的主存储单元中的数据元素可以要求以受控的方式改变该数据元素。因为其他数据处理单元可以访问该数据元素，所以数据元素的改变必须被同步，以便其他数据处理单元不会同时改变相同的数据元素。本发明包括获取对主存储器单元中的联锁信号的访问并且在主存储器单元中启动互锁的指令，从而排除其他数据处理单元以同时访问互锁信号。该指令使与互锁信号相关的数据元素被传送到数据元素被保存的数据处理单元，可以进入掩模装置，然后添加一个数量。更改的数据元素返回到主存储器单元位置，并且主存储器互锁信号被释放，从而完成指令。

4. 发明授权

US5193167A Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system 失效
标题翻译：通过多载波系统中的锁定负载和条件存储操作来保证数据的完整性
公开(公告)号：US5193167A
公开(公告)日：1993-03-09
申请号：US547618
申请日：1990-06-29
申请人： Richard L. Sites , Richard T. Witek
发明人： Richard L. Sites , Richard T. Witek
IPC分类号： G06F9/305 , G06F9/30 , G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/383 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

5. 发明授权

US5454091A Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed 失效
标题翻译：虚拟到物理地址转换方案，其粒度提示用于识别要访问的后续页面
公开(公告)号：US5454091A
公开(公告)日：1995-09-26
申请号：US111284
申请日：1993-08-24
申请人： Richard L. Sites , Richard T. Witek
发明人： Richard L. Sites , Richard T. Witek
IPC分类号： G06F9/34 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F2212/652
摘要： A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.
摘要翻译：精简指令集（RISC）类型的高性能中央处理单元（CPU）采用标准化的固定指令大小，仅允许简化的存储器访问数据宽度和寻址模式。指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。处理器可以采用可变存储器页面大小，使得可以最佳地使用用于实现虚拟寻址的翻译缓冲器中的条目。在页表项中添加了粒度提示，以定义此条目的页面大小。

6. 发明授权

US5430888A Pipeline utilizing an integral cache for transferring data to and from a register 失效
标题翻译：管道利用集成缓存将数据传送到寄存器和从寄存器传输数据
公开(公告)号：US5430888A
公开(公告)日：1995-07-04
申请号：US143509
申请日：1993-10-26
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
摘要翻译：用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。流水线包括支持多个未完成读请求未命中的缓冲区。来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。然后可以用所请求的数据填充高速缓存存储器。在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

7. 发明授权

US5148544A Apparatus and method for control of asynchronous program interrupt events in a data processing system 失效
标题翻译：用于在数据处理系统中控制异步程序中断事件的装置和方法
公开(公告)号：US5148544A
公开(公告)日：1992-09-15
申请号：US704710
申请日：1991-05-17
申请人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
发明人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
IPC分类号： G06F9/30 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/30076
摘要： In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode. The pending interrupt condition and the request registers may be accessed only from the privileged mode of operation.
摘要翻译：在具有内核模式（即，用于执行特许指令）和用户操作模式的数据处理系统中，用于响应中断条件的装置包括第一寄存器，受到当前正在执行的程序的控制以使能生成模式相关中断信号，并且包括用于指示存在待决模式相关中断条件的第二寄存器，并且用于请求模式相关中断的第三寄存器被输入到第二寄存器中。监视操作模式和使能和待处理中断条件寄存器，并且当两个寄存器中的信号具有适当的关系时，产生一个控制程序将响应的中断信号。第一寄存器的内容可以由当前执行的程序控制，该程序可以控制当前执行模式的使能信号。挂起的中断条件和请求寄存器只能从特权操作模式访问。

8. 发明授权

US5148536A Pipeline having an integral cache which processes cache misses and loads data in parallel 失效
标题翻译：具有整合速度的流水线，并行处理缓存和负载数据
公开(公告)号：US5148536A
公开(公告)日：1992-09-15
申请号：US224483
申请日：1988-07-25
申请人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
发明人： Richard T. Witek , Douglas D. Williams , Timothy J. Stanley , David M. Fenwick , Douglas J. Burns , Rebecca L. Stamm , Richard Heye
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0859 , G06F15/8084 , G06F9/383
摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

9. 发明授权

US5063497A Apparatus and method for recovering from missing page faults in vector data processing operations 失效
标题翻译：用于从向量数据处理操作中的错误页面错误中恢复的装置和方法
公开(公告)号：US5063497A
公开(公告)日：1991-11-05
申请号：US69372
申请日：1987-07-01
申请人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
发明人： David N. Cutler , David A. Orbits , Dileep Bhandarkar , Wayne Cardoza , Richard T. Witek
IPC分类号： G06F9/38 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F9/3865 , G06F12/08 , G06F15/8069 , G06F9/30036
摘要： In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

10. 发明授权

US07750912B2 Integrating display controller into low power processor 有权
标题翻译：将显示控制器集成到低功耗处理器中
公开(公告)号：US07750912B2
公开(公告)日：2010-07-06
申请号：US11286690
申请日：2005-11-23
申请人： R. Stephen Polzin , Richard T. Witek , Maurice B. Steinman
发明人： R. Stephen Polzin , Richard T. Witek , Maurice B. Steinman
IPC分类号： G09G5/36
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3218 , G06F1/325 , G06F15/7807 , Y02D10/122 , Y02D50/20
摘要： In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.
摘要翻译：在一个实施例中，系统包括存储器; 耦合到存储器的存储器接口; 耦合到存储器接口的处理器单元，耦合到处理器单元的第二接口和图形处理单元。处理器单元包括至少一个处理器核心和被配置为耦合到显示器的显示控制器。图形处理单元被配置为将数据呈现到表示要在显示器上显示的图像的帧缓冲器。如果图形处理单元不呈现，则处理器单元被配置为停用第二接口，并且即使第二接口被停用，显示控制器被配置为读取用于显示的帧缓冲器数据以进行显示。

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