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1. 发明授权

US06360285B1 Apparatus for determining memory bank availability in a computer system 失效
标题翻译：用于确定计算机系统中的存储体可用性的装置
公开(公告)号：US06360285B1
公开(公告)日：2002-03-19
申请号：US08269234
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
发明人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
IPC分类号： G06F1202
CPC分类号： G06F13/16
摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.
摘要翻译：根据本发明，一种装置包括具有存储体可用信号的系统总线。耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制。通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

2. 发明授权

US6076129A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US6076129A
公开(公告)日：2000-06-13
申请号：US869610
申请日：1997-06-06
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

3. 发明授权

US5666551A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US5666551A
公开(公告)日：1997-09-09
申请号：US590802
申请日：1996-01-24
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。用于跟踪在总线上发生的地址和命令事务的机制针对地址总线上发生的每个地址和命令事务产生相应的序列号标签。由数据总线排序器存储与节点发起数据事务的地址和命令事务对应的那些序列号标签。数据总线序列器还包括用于对在数据总线上发生的数据事务的数量进行计数的电路，将计数的数据事务数与存储的序列号标签进行比较，并响应于该比较在数据总线上启动数据事务。

4. 发明授权

US5475690A Delay compensated signal propagation 失效
标题翻译：延迟补偿信号传播
公开(公告)号：US5475690A
公开(公告)日：1995-12-12
申请号：US337352
申请日：1994-11-10
申请人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
发明人： Douglas J. Burns , David M. Fenwick , Ricky C. Hetherington
IPC分类号： G06F13/42 , H04J3/06
CPC分类号： G06F13/4239
摘要： In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.
摘要翻译：在计算机系统中，数字信号从输出寄存器发送，沿着第一信令路径传播并由输入寄存器接收。信令路径包括地址缓冲器，高速缓冲存储器，主存储器和互连网络。数字信号经历的固有延迟的影响被测量为相对于通过复制第一信令路径的延迟的第二信令路径传播的参考时钟信号的延迟值。延迟值用于选择性地延迟数字信号以保持发送和接收的数字信号之间的固定关系。延迟测量和调节通过驱动参考和数字信号通过类似的抽头延迟线，即延迟线的输出抽头控制延迟线的输出抽头来提供。提供存储锁存器以将测量的延迟值保持在连续采样之间。

5. 发明授权

US07873776B2 Multiple-core processor with support for multiple virtual processors 有权
标题翻译：多核处理器支持多个虚拟处理器
公开(公告)号：US07873776B2
公开(公告)日：2011-01-18
申请号：US11063793
申请日：2005-02-23
申请人： Ricky C. Hetherington , Bikram Saha
发明人： Ricky C. Hetherington , Bikram Saha
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/3879 , G06F9/3891 , G06F9/45533
摘要： A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and core/bank mapping logic coupled to the cache banks and processor cores. During a first mode of processor operation, each of the processor cores may be configurable to access any of the cache banks, and during a second mode of processor operation, the core/bank mapping logic may be configured to implement a plurality of virtual processors within the processor. A first virtual processor may include a first subset of the processor cores and a first subset of the banks, and a second virtual processor may include a second subset of the processor cores and a second subset of the cache banks. Subsets of processor cores and cache banks included in the first and second virtual processors may be distinct.
摘要翻译：支持多个虚拟处理器的多核处理器。在一个实施例中，处理器可以包括包括多个高速缓存组，多个处理器核心以及耦合到高速缓存组和处理器核心的核心/组映射逻辑的高速缓存。在处理器操作的第一模式期间，每个处理器核可以被配置为访问任何高速缓存组，并且在处理器操作的第二模式期间，核心/库映射逻辑可以被配置为在多个虚拟处理器内实现多个虚拟处理器处理器。第一虚拟处理器可以包括处理器核心的第一子集和存储体的第一子集，并且第二虚拟处理器可以包括处理器核心的第二子集和高速缓存组的第二子集。包括在第一和第二虚拟处理器中的处理器核心和高速缓存组的子集可以是不同的。

6. 发明授权

US07685354B1 Multiple-core processor with flexible mapping of processor cores to cache banks 有权
标题翻译：多核处理器具有处理器内核与缓存存储库的灵活映射
公开(公告)号：US07685354B1
公开(公告)日：2010-03-23
申请号：US11063792
申请日：2005-02-23
申请人： Ricky C. Hetherington , Manish K. Shah , Gregory F. Grohoski , Bikram Saha
发明人： Ricky C. Hetherington , Manish K. Shah , Gregory F. Grohoski , Bikram Saha
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/084 , G06F12/0846 , G06F2212/601
摘要： A multiple-core processor providing flexible mapping of processor cores to cache banks. In one embodiment, a processor may include a cache including a number of cache banks. The processor may further include a number of processor cores configured to access the cache banks, as well as core/bank mapping logic coupled to the cache banks and processor cores. The core/bank mapping logic may be configurable to map a cache bank select portion of a memory address specified by a given one of the processor cores to any one of the cache banks.
摘要翻译：多核处理器提供处理器内核到缓存存储库的灵活映射。在一个实施例中，处理器可以包括包括多个高速缓存组的高速缓存。处理器还可以包括被配置为访问高速缓存组的多个处理器核以及耦合到高速缓冲存储器组和处理器核的核心/库映射逻辑。核心/库映射逻辑可以被配置为将由给定的一个处理器核心指定的存储器地址的高速缓存存储体选择部分映射到任何一个高速缓存存储体。

7. 发明授权

US07644221B1 System interface unit 有权
标题翻译：系统接口单元
公开(公告)号：US07644221B1
公开(公告)日：2010-01-05
申请号：US11103319
申请日：2005-04-11
申请人： Paul G. Chan , Ricky C. Hetherington
发明人： Paul G. Chan , Ricky C. Hetherington
IPC分类号： G06F13/36
CPC分类号： G06F13/387
摘要： A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions. In addition, each of the I/O units may also indicate in the common format whether a given transaction is to be ordered with respect to other transactions. The system interface may separately store ordered transactions from those which are non-ordered.
摘要翻译：一种处理器，包括被配置为管理多个I / O接口和多个协议的集成系统接口单元。处理器包括多个处理核心，包括多个存储体的高速缓存以及耦合到处理核心和高速缓存的系统接口单元。系统接口单元包括配置成从第一I / O单元和第二I / O单元接收入站事务的入站单元，以及配置为将出站事务传送到第一I / O单元或第二I / O单位。第一和第二I / O单元中的每一个被配置为支持不同的协议。在将交易数据传送到系统接口之前，第一个I / O单元和第二个I / O单元重新格式化交易数据以符合通用格式。系统接口将事务数据接收并存储在专用于可缓存事务的队列或专用于不可缓存事务的队列中。此外，每个I / O单元还可以以通用格式指示给定的交易是否相对于其他交易被排序。系统接口可以分别存储有序的事务和非有序事务。

8. 发明授权

US07587658B1 ECC encoding for uncorrectable errors 有权
标题翻译： ECC编码用于不可纠正的错误
公开(公告)号：US07587658B1
公开(公告)日：2009-09-08
申请号：US11028703
申请日：2005-01-03
申请人： Ye Tong , Ricky C. Hetherington
发明人： Ye Tong , Ricky C. Hetherington
IPC分类号： H03M13/00
CPC分类号： G06F11/1012
摘要： An error detecting and correcting method and mechanism. An error correcting code for data is utilized wherein a special syndrome pattern is used to indicate corresponding data includes a previously detected uncorrectable error. In response to receiving data and corresponding first check bits from a storage device, new check bits corresponding to the read data are generated. Based upon the read check bits and newly generated check bits, a syndrome is generated. If an uncorrectable error is detected, the newly generated check bits are inverted prior to be stored. Subsequent readers of the stored data will generate a syndrome which corresponds to the predetermined pattern and determine that the data includes a previously detected uncorrectable error. Data including an error corresponding to an previously detected uncorrectable error may be discarded and no error reported.
摘要翻译：一种误差检测和校正方法及机理。使用用于数据的纠错码，其中使用特殊的校正码模式来指示对应的数据包括先前检测到的不可校正的错误。响应于来自存储设备的接收数据和对应的第一校验位，生成与读取数据相对应的新校验位。基于读取校验位和新产生的校验位，产生校正子。如果检测到不可校正的错误，则新生成的校验位在被存储之前被反转。存储数据的后续读取器将产生对应于预定模式的校正子，并确定数据包括先前检测到的不可校正错误。包括与先前检测到的不可校正错误相对应的错误的数据可能被丢弃，并且不报告错误。

9. 发明授权

US06269426B1 Method for operating a non-blocking hierarchical cache throttle 失效
标题翻译：用于操作非阻塞分级缓存节流阀的方法
公开(公告)号：US06269426B1
公开(公告)日：2001-07-31
申请号：US08881724
申请日：1997-06-24
申请人： Ricky C. Hetherington , Thomas M. Wicki
发明人： Ricky C. Hetherington , Thomas M. Wicki
IPC分类号： G06F1208
CPC分类号： G06F12/0897
摘要： A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level. In response to the monitoring step the second cache level generates a stall signal thereby stalling the picking process.
摘要翻译：用于操作多级缓存的多级缓存和方法，其同时生成多个高速缓存系统访问。每个访问请求包括标识具有作为访问目标的数据的存储器位置的地址。插入指针将每个访问请求插入到内存调度窗口中的条目中。当该条目准备好应用于第一个缓存级别时，每个条目都将被标记为有效。选择器通过指向所选择的条目并将其中的地址应用于第一高速缓存级别从存储器调度窗口中选择有效条目。无论访问是否在第一个高速缓存级别中，都会以自由运行模式进行选择。第二缓存级别，接收在第一高速缓存级别中丢失的访问。第二高速缓存级别中的资源监视器确定预定数量的资源何时被提交到服务于在第一高速缓存级别中错过的访问。响应于监视步骤，第二高速缓存级别产生失速信号，从而停止拾取过程。

10. 发明授权

US6081873A In-line bank conflict detection and resolution in a multi-ported non-blocking cache 失效
标题翻译：多端口非阻塞缓存中的在线银行冲突检测和解析
公开(公告)号：US6081873A
公开(公告)日：2000-06-27
申请号：US881065
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0851
摘要： A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的较低级别的设备接收数据访问请求的多端口非阻塞高速缓存。存储器调度窗口包括至少一行条目，其中每个条目包括保存访问请求的地址的地址字段。至少一些条目内的冲突映射字段被耦合到冲突检查单元。冲突检查单元通过设置冲突映射字段中的位来指示地址字段以指示条目之间的行内冲突。耦合到存储器调度窗口的选择器响应于冲突映射字段，以便识别在多端口非阻塞高速缓存上并行启动的非冲突条目的组。

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