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1. 发明授权

US06256694B1 Distributed early arbitration 失效
标题翻译：分散的早期仲裁
公开(公告)号：US06256694B1
公开(公告)日：2001-07-03
申请号：US08269251
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F1336
CPC分类号： G06F13/36 , G06F12/0884 , G06F13/368
摘要： A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.
摘要翻译：一个指挥官模块，其耦合到包括系统总线控制请求信号并与系统总线控制请求信号之一相关联的系统总线，包括用于确定是否需要控制系统总线的装置，以及用于请求控制系统总线的装置以通过断言相关的系统总线控制请求信号来确定是否需要这样的控制。包括系统总线和耦合到系统总线的至少两个这样的指挥器模块的计算机系统以及用于仲裁以控制系统总线的装置，其中仲裁装置耦合到并且响应于系统总线控制请求信号。

2. 发明授权

US5758106A Arbitration unit which requests control of the system bus prior to determining whether such control is required 失效
标题翻译：在确定是否需要此类控制之前，要求对系统总线进行控制的仲裁单元
公开(公告)号：US5758106A
公开(公告)日：1998-05-26
申请号：US741084
申请日：1996-10-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F13/368 , G06F13/36
CPC分类号： G06F13/368
摘要： A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.
摘要翻译：一种指挥官模块，包括用于确定是否需要控制系统总线的装置，用于在确定是否需要这种控制之前请求对系统总线的控制的装置，以及响应于确定装置指示系统的控制的装置公车是必需的。一种计算机系统，包括系统总线和耦合到系统总线的至少两个这样的指挥器模块，并且包括用于仲裁用于系统总线控制的装置，包括用于将系统总线的控制授权给指令器模块之一，指示控制系统总线是必需的，并且在这些指挥器模块中具有最高的仲裁优先级，还指示需要对系统总线的控制。

3. 发明授权

US5566325A Method and apparatus for adaptive memory access 失效
标题翻译：用于自适应存储器访问的方法和装置
公开(公告)号：US5566325A
公开(公告)日：1996-10-15
申请号：US269259
申请日：1994-06-30
申请人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G11C7/22 , G11C8/18 , G06F12/00 , G06F1/12
CPC分类号： G11C8/18 , G11C7/22
摘要： A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.
摘要翻译：提供了一种存储器系统，其可以适应于耦合到能够以不同时钟速度运行的总线。存储器系统响应由总线速度传感器提供的信号，用于修改行地址选通（RAS），列地址选通（CAS）和写使能（WE）信号的定时。通过修改RAS，CAS和WE信号的时序，可以在能够以各种总线速度工作的系统中操作存储器，而不会遇到通常与总线速度变化相关的延迟问题。

4. 发明授权

US5848258A Memory bank addressing scheme 失效
标题翻译：存储库寻址方案
公开(公告)号：US5848258A
公开(公告)日：1998-12-08
申请号：US711387
申请日：1996-09-06
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren , Dave Hartwell
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren , Dave Hartwell
IPC分类号： G06F12/06 , G06F12/02
CPC分类号： G06F12/0607 , G06F12/0661
摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory. Further, the apparatus allows memory modules having a different number of memory banks and memory banks capable of storing a different number of addressable locations to be efficiently used in the same computer system.
摘要翻译：根据本发明，一种装置包括具有存储体识别信号的系统总线。耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体和至少一个指令器模块。指挥官模块包含解码逻辑，其包括与要在存储体识别信号上驱动的唯一值相关联的存储器映射寄存器。存储器组包含比较逻辑，包括虚拟节点识别寄存器，其存储要与存储器组标识信号驱动的值进行比较的预定值，以确定存储体是否为当前事务的目标。因此，存储器库不需要解码整个系统总线地址，以确定它们是否是事务的目标，这减少了与存储器完成交易所需的时间。此外，该装置允许具有不同数量的存储体的存储器模块和能够存储不同数量的可寻址位置以在同一计算机系统中有效使用的存储器组。

5. 发明授权

US5761731A Method and apparatus for performing atomic transactions in a shared memory multi processor system 失效
标题翻译：在共享存储器多处理器系统中执行原子事务的方法和装置
公开(公告)号：US5761731A
公开(公告)日：1998-06-02
申请号：US859462
申请日：1997-05-19
申请人： Stephen R. Van Doren , Denis Foley , David M. Fenwick
发明人： Stephen R. Van Doren , Denis Foley , David M. Fenwick
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1647
摘要： A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.sub.-- BANK.sub.-- UNLOCK instruction. The WRITE.sub.-- BANK.sub.-- UNLOCK instruction updates memory with the modified data and the bank busy bit is set to indicate availability of the bank to other nodes on the bus.
摘要翻译：用于确保通过多处理器系统中的公共互连耦合到存储器的多个节点准确和及时地完成原子事务的机制包括耦合到总线的多个节点，所述多个节点包括存储器节点，I / O节点，和处理器节点。存储器节点分别分配成多个存储体并且一起构成存储器。与每个银行相关联的是一个繁忙的信号，指示存储器的可用性用于交易。节点可以通过使用READ-BANK-LOCK和WRITE-BANK-UNLOCK指令向存储器数据块发出原子事务。执行原子事务的节点监视银行的忙信号的状态，并且当银行可用时，节点发出READ-BANK-LOCK指令，其将忙位设置为指示银行的不可用性。 READ-BANK-LOCK指令完成后，节点发出WRITE-BANK-UNLOCK指令。 WRITE-BANK-UNLOCK指令用修改后的数据更新存储器，并将存储区忙位设置为指示存储体对总线上其他节点的可用性。

6. 发明授权

US5737546A System bus with separate address and data bus protocols 失效
标题翻译：系统总线具有独立的地址和数据总线协议
公开(公告)号：US5737546A
公开(公告)日：1998-04-07
申请号：US775552
申请日：1996-12-31
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
IPC分类号： G06F13/42 , G06F13/00 , G06F13/368
CPC分类号： G06F13/4213
摘要： Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.
摘要翻译：耦合到计算机系统中的系统总线的节点的总线接口，系统总线包括地址总线和单独的数据总线。系统总线操作包括地址和命令事务和数据事务。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。总线接口可以包括用于向地址总线地址和命令事务提供的指挥官地址总线接口装置中的任一个，用于通过地址总线确认接收地址和命令事务的响应方地址总线接口装置，用于由于在地址总线上发生地址和命令事务而导致数据事务的数据总线的提交;以及响应者数据总线接口装置，用于在数据事务期间在数据总线上传送数据。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。特别地，数据事务的定时和数据事务在数据总线上发生的速率与地址和命令事务的定时以及地址总线上发生地址子事务的速率无关。

7. 发明授权

US6076129A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US6076129A
公开(公告)日：2000-06-13
申请号：US869610
申请日：1997-06-06
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

8. 发明授权

US5666551A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US5666551A
公开(公告)日：1997-09-09
申请号：US590802
申请日：1996-01-24
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。用于跟踪在总线上发生的地址和命令事务的机制针对地址总线上发生的每个地址和命令事务产生相应的序列号标签。由数据总线排序器存储与节点发起数据事务的地址和命令事务对应的那些序列号标签。数据总线序列器还包括用于对在数据总线上发生的数据事务的数量进行计数的电路，将计数的数据事务数与存储的序列号标签进行比较，并响应于该比较在数据总线上启动数据事务。

9. 发明授权

US5537575A System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information 失效
标题翻译：用于处理高速缓存存储器受害者数据的系统，该缓冲存储器将数据从高速缓存传送到接口，而CPU使用高速缓存状态信息执
公开(公告)号：US5537575A
公开(公告)日：1996-07-16
申请号：US268403
申请日：1994-06-30
申请人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
发明人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus. In response to the command for transmitting cache memory victim data, the cache memory data which is waiting in the data interface, is transmitted from the data interface to main memory over the system bus.
摘要翻译：一种用于处理用于更新主存储器的高速缓存存储器受害数据的计算机系统中的方法和装置。本发明在具有通过根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块耦合到主存储器的计算机系统中操作。在执行了一个高速缓存存储器地址的READ的处理器中，对应于正在读取的高速缓存存储器地址的高速缓存存储器数据从高速缓冲存储器数据存储器发送到数据接口。高速缓存存储器数据在执行高速缓存存储器地址信息的READ期间被数据接口累积地接收。确定与高速缓存存储器地址相对应的高速缓存存储器数据是否为高速缓存存储器受害者。如果该确定确定它是缓存存储器受害者，则处理器通过系统总线发出用于将高速缓存存储器受害数据发送到主存储器的命令。响应于用于发送高速缓存存储器受害者数据的命令，在数据接口中等待的高速缓存存储器数据通过系统总线从数据接口发送到主存储器。

10. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

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