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1. 发明授权

US6122714A Order supporting mechanisms for use in a switch-based multi-processor system 失效
标题翻译：用于基于交换机的多处理器系统中的订单支持机制
公开(公告)号：US6122714A
公开(公告)日：2000-09-19
申请号：US957298
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
IPC分类号： G06F12/08 , G06F9/46 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

2. 发明授权

US06360285B1 Apparatus for determining memory bank availability in a computer system 失效
标题翻译：用于确定计算机系统中的存储体可用性的装置
公开(公告)号：US06360285B1
公开(公告)日：2002-03-19
申请号：US08269234
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
发明人： David M. Fenwick , Denis Foley , David Hartwell , Ricky C. Hetherington , Dale R. Keck , Elbert Bloom
IPC分类号： G06F1202
CPC分类号： G06F13/16
摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.
摘要翻译：根据本发明，一种装置包括具有存储体可用信号的系统总线。耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制。通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

3. 发明授权

US5179674A Method and apparatus for predicting valid performance of virtual-address to physical-address translations 失效
标题翻译：用于预测虚拟地址到物理地址转换的有效性能的方法和装置
公开(公告)号：US5179674A
公开(公告)日：1993-01-12
申请号：US224443
申请日：1988-07-25
申请人： Douglas D. Williams , David M. Fenwick , Timothy J. Stanley
发明人： Douglas D. Williams , David M. Fenwick , Timothy J. Stanley
IPC分类号： G06F12/08 , G06F12/10 , G06F17/16
CPC分类号： G06F12/10 , G06F2212/655
摘要： A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

4. 发明授权

US5175613A Package for EMI, ESD, thermal, and mechanical shock protection of circuit chips 失效
标题翻译：用于电路芯片的EMI，ESD，热和机械冲击保护的封装
公开(公告)号：US5175613A
公开(公告)日：1992-12-29
申请号：US644401
申请日：1991-01-18
申请人： Charles R. Barker, III , Richard J. Casabona , David M. Fenwick
发明人： Charles R. Barker, III , Richard J. Casabona , David M. Fenwick
IPC分类号： H01L23/00 , H01L23/32 , H01L23/367 , H01L23/552 , H01L23/60
CPC分类号： H01L23/562 , H01L23/32 , H01L23/3675 , H01L23/552 , H01L23/60 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/16152 , H01L2924/16251 , H01L2924/3025
摘要： A package for integrated circuit chips, or other electrical devices, provides mechanical shock and thermal protection for the chips, and in addition, protects the chips from electromagnetic interference and electrostatic discharge. The package includes a printed wiring board base for reception of one or more circuit chips, and a conductive heat sink and cover. The conductive heat sink, in conjunction with a reference plane in the wiring board base, acts as an EMI shield for the chips. The heat sink is covered with an insulating layer, on top of which, a conductive coating is placed. The conductive coating is electrically connected to the reference plane, and the two act to protect the chips from electrostatic discharges. Compliant pads support the chips, and a thermally conductive elastomer can be placed on top of each chip between the chips and the inner top surface of the heat sink. The chips are thereby held securely in position, and are thermally connected to the heat sink.
摘要翻译：用于集成电路芯片或其他电气设备的封装为芯片提供机械冲击和热保护，此外，保护芯片免受电磁干扰和静电放电。该封装包括用于接收一个或多个电路芯片的印刷线路板基座和导电散热器和盖。导电散热器与布线板底座中的参考平面结合，用作芯片的EMI屏蔽。散热器被绝缘层覆盖，其上放置导电涂层。导电涂层电连接到参考平面，两者用于保护芯片免受静电放电。兼容焊盘支持芯片，并且导热弹性体可以放置在芯片和散热器的内顶表面之间的每个芯片的顶部。因此，芯片牢固地保持在适当位置，并且热连接到散热器。

5. 发明授权

US06256694B1 Distributed early arbitration 失效
标题翻译：分散的早期仲裁
公开(公告)号：US06256694B1
公开(公告)日：2001-07-03
申请号：US08269251
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F1336
CPC分类号： G06F13/36 , G06F12/0884 , G06F13/368
摘要： A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.
摘要翻译：一个指挥官模块，其耦合到包括系统总线控制请求信号并与系统总线控制请求信号之一相关联的系统总线，包括用于确定是否需要控制系统总线的装置，以及用于请求控制系统总线的装置以通过断言相关的系统总线控制请求信号来确定是否需要这样的控制。包括系统总线和耦合到系统总线的至少两个这样的指挥器模块的计算机系统以及用于仲裁以控制系统总线的装置，其中仲裁装置耦合到并且响应于系统总线控制请求信号。

6. 发明授权

US6076129A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US6076129A
公开(公告)日：2000-06-13
申请号：US869610
申请日：1997-06-06
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

7. 发明授权

US5758106A Arbitration unit which requests control of the system bus prior to determining whether such control is required 失效
标题翻译：在确定是否需要此类控制之前，要求对系统总线进行控制的仲裁单元
公开(公告)号：US5758106A
公开(公告)日：1998-05-26
申请号：US741084
申请日：1996-10-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F13/368 , G06F13/36
CPC分类号： G06F13/368
摘要： A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.
摘要翻译：一种指挥官模块，包括用于确定是否需要控制系统总线的装置，用于在确定是否需要这种控制之前请求对系统总线的控制的装置，以及响应于确定装置指示系统的控制的装置公车是必需的。一种计算机系统，包括系统总线和耦合到系统总线的至少两个这样的指挥器模块，并且包括用于仲裁用于系统总线控制的装置，包括用于将系统总线的控制授权给指令器模块之一，指示控制系统总线是必需的，并且在这些指挥器模块中具有最高的仲裁优先级，还指示需要对系统总线的控制。

8. 发明授权

US5566325A Method and apparatus for adaptive memory access 失效
标题翻译：用于自适应存储器访问的方法和装置
公开(公告)号：US5566325A
公开(公告)日：1996-10-15
申请号：US269259
申请日：1994-06-30
申请人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G11C7/22 , G11C8/18 , G06F12/00 , G06F1/12
CPC分类号： G11C8/18 , G11C7/22
摘要： A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.
摘要翻译：提供了一种存储器系统，其可以适应于耦合到能够以不同时钟速度运行的总线。存储器系统响应由总线速度传感器提供的信号，用于修改行地址选通（RAS），列地址选通（CAS）和写使能（WE）信号的定时。通过修改RAS，CAS和WE信号的时序，可以在能够以各种总线速度工作的系统中操作存储器，而不会遇到通常与总线速度变化相关的延迟问题。

9. 发明授权

US5737546A System bus with separate address and data bus protocols 失效
标题翻译：系统总线具有独立的地址和数据总线协议
公开(公告)号：US5737546A
公开(公告)日：1998-04-07
申请号：US775552
申请日：1996-12-31
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
IPC分类号： G06F13/42 , G06F13/00 , G06F13/368
CPC分类号： G06F13/4213
摘要： Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.
摘要翻译：耦合到计算机系统中的系统总线的节点的总线接口，系统总线包括地址总线和单独的数据总线。系统总线操作包括地址和命令事务和数据事务。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。总线接口可以包括用于向地址总线地址和命令事务提供的指挥官地址总线接口装置中的任一个，用于通过地址总线确认接收地址和命令事务的响应方地址总线接口装置，用于由于在地址总线上发生地址和命令事务而导致数据事务的数据总线的提交;以及响应者数据总线接口装置，用于在数据事务期间在数据总线上传送数据。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。特别地，数据事务的定时和数据事务在数据总线上发生的速率与地址和命令事务的定时以及地址总线上发生地址子事务的速率无关。

10. 发明授权

US5625805A Clock architecture for synchronous system bus which regulates and adjusts clock skew 失效
标题翻译：同步系统总线的时钟架构，可调节和调整时钟偏移
公开(公告)号：US5625805A
公开(公告)日：1997-04-29
申请号：US269223
申请日：1994-06-30
申请人： David M. Fenwick , Daniel Wissell , Richard Watson , Denis Foley
发明人： David M. Fenwick , Daniel Wissell , Richard Watson , Denis Foley
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.
摘要翻译：描述了同步计算机系统。该系统是具有总线系统时钟和每个处理器的处理器时钟的多处理器系统。该系统包括同步计算机系统总线和耦合到同步总线的多个电路模块，其中至少两个模块具有至少一个处理器，处理器模块具有至少一个处理器，其与另一个处理器异步运行处理器，而处理器模块与系统总线同步。该系统还包括用于提供对应的多个时钟信号的时钟发生器装置和耦合在所述时钟发生装置和所述多个模块之间的多个导体。每个所述导体具有基本上相同的电路径长度的电路径，其中每个所述模块还包括耦合到所述导体中的相应一个导体并设置在所述模块上的装置，用于调节和调整所述模块上的时钟信号之间的偏差。

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