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1. 发明授权

US06812524B2 Field effect controlled semiconductor component 有权
标题翻译：场效应控制半导体元件
公开(公告)号：US06812524B2
公开(公告)日：2004-11-02
申请号：US10013999
申请日：2001-12-11
申请人： Dirk Ahlers , Jens-Peer Stengl , Jenoe Tihanyi , Hans Weber , Gerald Deboy , Helmut Strack , Armin Willmeroth
发明人： Dirk Ahlers , Jens-Peer Stengl , Jenoe Tihanyi , Hans Weber , Gerald Deboy , Helmut Strack , Armin Willmeroth
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/7816
摘要： A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the semiconductor body, and a drift path that is formed between the channel zone and the first connection zone and contains a compensation zone. The compensation zone has a complementary conduction type with respect to the drift zone and includes at least two segments. A distance between the two adjacent segments is chosen such that the punch-through voltage between these segments lies in a voltage range that corresponds to the voltage range assumed by the voltage drop across the drift path at currents situated between the rated current and twice the rated current.
摘要翻译：半导体部件包括形成在半导体本体中的第一和第二连接区域，围绕半导体主体中的第二连接区域的沟道区域以及形成在沟道区域和第一连接区域之间并且包含补偿区域的漂移路径。补偿区相对于漂移区具有互补导电类型并且包括至少两个段。选择两个相邻段之间的距离，使得这些段之间的穿通电压位于对应于位于额定电流和额定电流两倍之间的电流处的漂移路径上的电压降所假定的电压范围的电压范围当前。

2. 发明授权

US06667514B2 Semiconductor component with a charge compensation structure and associated fabrication 有权
标题翻译：具有电荷补偿结构和相关制造的半导体元件
公开(公告)号：US06667514B2
公开(公告)日：2003-12-23
申请号：US10190119
申请日：2002-07-03
申请人： Dirk Ahlers , Gerald Deboy , Hans Weber , Armin Willmeroth
发明人： Dirk Ahlers , Gerald Deboy , Hans Weber , Armin Willmeroth
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/41766
摘要： A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge region of the charge compensation structure. Thus, an electrical parameter such as the on resistance of the semiconductor component can be substantially improved without influencing or impairing further parameters such as the breakdown voltage and the robustness with respect to TRAPATT oscillations. Methods of fabricating a semiconductor component with a charge compensation structure are also provided.
摘要翻译：半导体部件包括电荷补偿结构，其中具有最大局部场强的位置位于电荷补偿结构的补偿边缘区域中。因此，可以显着地改善诸如半导体部件的导通电阻的电参数，而不影响或削弱诸如击穿电压和相对于TRAPATT振荡的鲁棒性的其它参数。还提供了制造具有电荷补偿结构的半导体部件的方法。

3. 发明授权

US06639272B2 Charge compensation semiconductor configuration 有权
公开(公告)号：US06639272B2
公开(公告)日：2003-10-28
申请号：US10113343
申请日：2002-04-01
申请人： Dirk Ahlers , Armin Willmeroth , Hans Weber
发明人： Dirk Ahlers , Armin Willmeroth , Hans Weber
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/66712
摘要： Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation regions.

4. 发明授权

US07038272B2 Method for forming a channel zone of a transistor and NMOS transistor 失效
标题翻译：用于形成晶体管和NMOS晶体管的沟道区的方法
公开(公告)号：US07038272B2
公开(公告)日：2006-05-02
申请号：US10631350
申请日：2003-07-31
申请人： Hans Weber , Dirk Ahlers , Uwe Wahl , Jenö Tihanyi , Armin Willmeroth
发明人： Hans Weber , Dirk Ahlers , Uwe Wahl , Jenö Tihanyi , Armin Willmeroth
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/7395 , H01L29/7816
摘要： In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the polysilicon layer with holes in a gate region and pillars in a source region enables the channel zone to be doped more lightly. In another embodiment, the novel method is used for a channel width shading of a PMOS transistor cell.
摘要翻译：在场效应晶体管中形成沟道区的方法中，在要形成的沟道区之上形成多晶硅层。多晶硅层用作用于随后掺杂沟道区的掩模基板。在栅极区域中具有空穴的多晶硅层的有利图案化以及源极区域中的柱状物使得能够更容易地掺杂沟道区。在另一个实施例中，新颖的方法用于PMOS晶体管单元的沟道宽度阴影。

5. 发明授权

US07332788B2 Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it 有权
标题翻译：具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法
公开(公告)号：US07332788B2
公开(公告)日：2008-02-19
申请号：US10927270
申请日：2004-08-26
申请人： Dirk Ahlers , Miguel Cuadron Marion , Uwe Wahl , Armin Willmeroth
发明人： Dirk Ahlers , Miguel Cuadron Marion , Uwe Wahl , Armin Willmeroth
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L27/0883 , H01L29/0634 , H01L29/0646 , H01L29/66712
摘要： The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complimentarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complimentarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).
摘要翻译：本发明涉及具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法。在该半导体功率器件的情况下，在芯片体积整体上配置垂直配置并与半导体芯片体积（5）相辅相成的电荷补偿单元（27）的区域（6），补充掺杂区域（6）延伸到半导体功率元件（7）的表面区域（11）中，并且不突出到半导体表面元件（1）的表面区域（12）中。

6. 发明申请

US20050045922A1 Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it 有权
标题翻译：具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法
公开(公告)号：US20050045922A1
公开(公告)日：2005-03-03
申请号：US10927270
申请日：2004-08-26
申请人： Dirk Ahlers , Miguel Marion , Uwe Wahl , Armin Willmeroth
发明人： Dirk Ahlers , Miguel Marion , Uwe Wahl , Armin Willmeroth
IPC分类号： H01L21/336 , H01L27/088 , H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7802 , H01L27/0883 , H01L29/0634 , H01L29/0646 , H01L29/66712
摘要： The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complementarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complementarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).
摘要翻译：本发明涉及具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法。在该半导体功率器件的情况下，在整个芯片体积上配置垂直配置并与半导体芯片体积（5）互补配置的电荷补偿单元（27）中的区域（6），互补掺杂区域（6）延伸到半导体功率元件（7）的表面区域（11）中，并且不突出到半导体表面元件（1）的表面区域（12）中。

7. 发明授权

US08803205B2 Transistor with controllable compensation regions 有权
标题翻译：具有可控补偿区域的晶体管
公开(公告)号：US08803205B2
公开(公告)日：2014-08-12
申请号：US13484490
申请日：2012-05-31
申请人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L27/088 , H01L27/098 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42356 , H01L29/7803 , H01L29/7831
摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
摘要翻译：半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接的MOSFET器件在负载端子之间。所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到晶体管器件的至少一个控制端子。

8. 发明授权

US07459365B2 Method for fabricating a semiconductor component 有权
标题翻译：半导体部件的制造方法
公开(公告)号：US07459365B2
公开(公告)日：2008-12-02
申请号：US11540922
申请日：2006-09-29
申请人： Michael Rüb , Herbert Schäfer , Armin Willmeroth , Anton Mauder , Stefan Sedlmaier , Roland Rupp , Manfred Pippan , Hans Weber , Frank Pfirsch , Franz Hirler , Hans-Joachim Schulze
发明人： Michael Rüb , Herbert Schäfer , Armin Willmeroth , Anton Mauder , Stefan Sedlmaier , Roland Rupp , Manfred Pippan , Hans Weber , Frank Pfirsch , Franz Hirler , Hans-Joachim Schulze
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/76224 , H01L29/0653 , H01L29/165 , H01L29/66734 , H01L29/7804 , H01L29/7849
摘要： The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.
摘要翻译：公开了具有半导体主体的半导体部件的制造，其中布置有具有在垂直方向上延伸并且非常深地延伸到半导体本体中的截面的非常薄的电介质层。在一种方法中，在从半导体主体的前侧开始的漂移区域中形成沟槽，在沟槽的至少一部分侧壁上产生牺牲层，并且沟槽的至少一部分填充有半导体材料被选择为使得沟槽中的半导体材料的净掺杂剂电荷的商和半导体材料和漂移区域之间的沟槽的侧壁上的牺牲层的总面积小于击穿电荷的半导体材料，并且牺牲层被电介质代替。

9. 发明申请

US20120305993A1 TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS 有权
标题翻译：具有可控制补偿区的晶体管
公开(公告)号：US20120305993A1
公开(公告)日：2012-12-06
申请号：US13484490
申请日：2012-05-31
申请人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/088 , H01L27/098 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42356 , H01L29/7803 , H01L29/7831
摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
摘要翻译：半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接的MOSFET器件在负载端子之间。所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到晶体管器件的至少一个控制端子。

10. 发明授权

US08866253B2 Semiconductor arrangement with active drift zone 有权
标题翻译：具有主动漂移区的半导体装置
公开(公告)号：US08866253B2
公开(公告)日：2014-10-21
申请号：US13362038
申请日：2012-01-31
申请人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
发明人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
IPC分类号： H01L27/00
CPC分类号： H01L27/0207 , H01L21/84 , H01L21/845 , H01L27/06 , H01L27/0629 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/4236 , H01L29/78 , H03K17/063 , H03K17/102
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二半导体器件，每个第二半导体器件具有在第一和第二负载端子与控制端子之间的负载路径。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子，并且其中一个第二半导体器件的控制端子连接到第一半导体器件的负载端子之一。每个第二半导体器件具有至少一个器件特性。第二半导体器件中的至少一个的至少一个器件特征与第二半导体器件中的其它器件的相应器件特性不同。

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