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1. 发明申请

US20130193525A1 Semiconductor Arrangement with Active Drift Zone 有权
公开(公告)号：US20130193525A1
公开(公告)日：2013-08-01
申请号：US13362038
申请日：2012-01-31
申请人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
发明人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L21/84 , H01L21/845 , H01L27/06 , H01L27/0629 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/4236 , H01L29/78 , H03K17/063 , H03K17/102
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

2. 发明授权

US08866253B2 Semiconductor arrangement with active drift zone 有权
标题翻译：具有主动漂移区的半导体装置
公开(公告)号：US08866253B2
公开(公告)日：2014-10-21
申请号：US13362038
申请日：2012-01-31
申请人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
发明人： Rolf Weis , Gerald Deboy , Michael Treu , Armin Willmeroth , Hans Weber
IPC分类号： H01L27/00
CPC分类号： H01L27/0207 , H01L21/84 , H01L21/845 , H01L27/06 , H01L27/0629 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/4236 , H01L29/78 , H03K17/063 , H03K17/102
摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.
摘要翻译：半导体器件布置包括具有负载路径的第一半导体器件和多个第二半导体器件，每个第二半导体器件具有在第一和第二负载端子与控制端子之间的负载路径。第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子，并且其中一个第二半导体器件的控制端子连接到第一半导体器件的负载端子之一。每个第二半导体器件具有至少一个器件特性。第二半导体器件中的至少一个的至少一个器件特征与第二半导体器件中的其它器件的相应器件特性不同。

3. 发明申请

US20120305993A1 TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS 有权
标题翻译：具有可控制补偿区的晶体管
公开(公告)号：US20120305993A1
公开(公告)日：2012-12-06
申请号：US13484490
申请日：2012-05-31
申请人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/088 , H01L27/098 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42356 , H01L29/7803 , H01L29/7831
摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
摘要翻译：半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接的MOSFET器件在负载端子之间。所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到晶体管器件的至少一个控制端子。

4. 发明授权

US08803205B2 Transistor with controllable compensation regions 有权
标题翻译：具有可控补偿区域的晶体管
公开(公告)号：US08803205B2
公开(公告)日：2014-08-12
申请号：US13484490
申请日：2012-05-31
申请人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L27/088 , H01L27/098 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42356 , H01L29/7803 , H01L29/7831
摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
摘要翻译：半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接的MOSFET器件在负载端子之间。所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到晶体管器件的至少一个控制端子。

5. 发明申请

US20110089481A1 MOS TRANSISTOR WITH ELEVATED GATE DRAIN CAPACITY 有权
标题翻译：具有高度门排水能力的MOS晶体管
公开(公告)号：US20110089481A1
公开(公告)日：2011-04-21
申请号：US12976107
申请日：2010-12-22
申请人： Armin Willmeroth , Michael Treu
发明人： Armin Willmeroth , Michael Treu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.
摘要翻译：描述了具有增加的栅 - 漏电容的MOS晶体管。一个实施例提供了第一导电类型的漂移区。至少一个晶体管单元具有体区，通过体区与漂移区分离的源极区以及邻近体区设置并通过栅介质与体区介电绝缘的栅电极。在漂移区域中布置有至少一个第一导电类型的补偿区域。至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。

6. 发明授权

US08421147B2 MOS transistor with elevated gate drain capacity 有权
标题翻译：具有提高的栅极漏极容量的MOS晶体管
公开(公告)号：US08421147B2
公开(公告)日：2013-04-16
申请号：US12976107
申请日：2010-12-22
申请人： Armin Willmeroth , Michael Treu
发明人： Armin Willmeroth , Michael Treu
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.
摘要翻译：描述了具有增加的栅 - 漏电容的MOS晶体管。一个实施例提供了第一导电类型的漂移区。至少一个晶体管单元具有体区，通过体区与漂移区分离的源极区以及邻近体区设置并通过栅介质与体区介电绝缘的栅电极。在漂移区域中布置有至少一个第一导电类型的补偿区域。至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。

7. 发明授权

US08492771B2 Heterojunction semiconductor device and method 有权
标题翻译：异质结半导体器件及方法
公开(公告)号：US08492771B2
公开(公告)日：2013-07-23
申请号：US11862661
申请日：2007-09-27
申请人： Michael Rüb , Michael Treu , Armin Willmeroth , Franz Hirler
发明人： Michael Rüb , Michael Treu , Armin Willmeroth , Franz Hirler
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/165 , H01L29/267 , H01L29/41775 , H01L29/66068
摘要： A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate. The first and second semiconductor regions are spaced in the first semiconductor substrate from each other in a direction parallel to the first plane by a first distance which is arranged in an area proximate to the heterojunction and which is larger than a second distance which is arranged in an area distal to the heterojunction.
摘要翻译：半导体器件包括第一带隙材料的第一半导体衬底和第二带隙材料的第二半导体衬底。第二带隙材料具有比第一带隙材料低的带隙。基本上在第一平面中，在第一半导体衬底和第二半导体衬底之间形成异质结。所述半导体器件还包括垂直于所述第一平面的横截面，所述第一导电类型的第一半导体区域和所述第一导电类型的第二半导体区域从所述第二半导体衬底至少部分地延伸进入第一半导体衬底。第一和第二半导体区域在第一半导体衬底中沿平行于第一平面的方向彼此间隔开第一距离，第一距离布置在接近异质结的区域中，并且大于第二距离远离异质结的区域。

8. 发明授权

US07910983B2 MOS transistor having an increased gate-drain capacitance 有权
标题翻译： MOS晶体管具有增加的栅 - 漏电容
公开(公告)号：US07910983B2
公开(公告)日：2011-03-22
申请号：US12241947
申请日：2008-09-30
申请人： Armin Willmeroth , Michael Treu
发明人： Armin Willmeroth , Michael Treu
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.
摘要翻译：描述了具有增加的栅 - 漏电容的MOS晶体管。一个实施例提供了第一导电类型的漂移区。至少一个晶体管单元具有体区，通过体区与漂移区分离的源极区以及邻近体区设置并通过栅介质与体区介电绝缘的栅电极。在漂移区域中布置有至少一个第一导电类型的补偿区域。至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。

9. 发明申请

US20100078708A1 MOS TRANSISTOR HAVING AN INCREASED GATE-DRAIN CAPACITANCE 有权
标题翻译：具有增加的栅极电容的MOS晶体管
公开(公告)号：US20100078708A1
公开(公告)日：2010-04-01
申请号：US12241947
申请日：2008-09-30
申请人： Armin Willmeroth , Michael Treu
发明人： Armin Willmeroth , Michael Treu
IPC分类号： H01L29/78 , H01L21/334
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which s dieletrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.
摘要翻译：描述了具有增加的栅 - 漏电容的MOS晶体管。一个实施例提供了第一导电类型的漂移区。至少一个晶体管单元具有体区，通过体区与漂移区分离的源区，以及栅电极，其邻近体区设置并且通过栅极电介质与体区隔离绝缘。在漂移区域中布置有至少一个第一导电类型的补偿区域。至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。

10. 发明申请

US20090184373A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090184373A1
公开(公告)日：2009-07-23
申请号：US12016478
申请日：2008-01-18
申请人： Winfried Kaindl , Michael Treu , Holger Kapels , Carolin Tolksdorf , Armin Willmeroth
发明人： Winfried Kaindl , Michael Treu , Holger Kapels , Carolin Tolksdorf , Armin Willmeroth
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/66712 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7803 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other.
摘要翻译：提供了具有半导体衬底的半导体器件。在半导体衬底中形成具有至少一个有源电池的活性电池区域，其中活性电池区域的至少一部分被边缘终止区域包围。至少部分地在所述边缘终端区域中布置集成门浇道结构，并且具有彼此串联电连接的至少一个低电阻部分和至少一个高电阻部分。

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