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1. 发明授权

US07459365B2 Method for fabricating a semiconductor component 有权
标题翻译：半导体部件的制造方法
公开(公告)号：US07459365B2
公开(公告)日：2008-12-02
申请号：US11540922
申请日：2006-09-29
申请人： Michael Rüb , Herbert Schäfer , Armin Willmeroth , Anton Mauder , Stefan Sedlmaier , Roland Rupp , Manfred Pippan , Hans Weber , Frank Pfirsch , Franz Hirler , Hans-Joachim Schulze
发明人： Michael Rüb , Herbert Schäfer , Armin Willmeroth , Anton Mauder , Stefan Sedlmaier , Roland Rupp , Manfred Pippan , Hans Weber , Frank Pfirsch , Franz Hirler , Hans-Joachim Schulze
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/76224 , H01L29/0653 , H01L29/165 , H01L29/66734 , H01L29/7804 , H01L29/7849
摘要： The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.
摘要翻译：公开了具有半导体主体的半导体部件的制造，其中布置有具有在垂直方向上延伸并且非常深地延伸到半导体本体中的截面的非常薄的电介质层。在一种方法中，在从半导体主体的前侧开始的漂移区域中形成沟槽，在沟槽的至少一部分侧壁上产生牺牲层，并且沟槽的至少一部分填充有半导体材料被选择为使得沟槽中的半导体材料的净掺杂剂电荷的商和半导体材料和漂移区域之间的沟槽的侧壁上的牺牲层的总面积小于击穿电荷的半导体材料，并且牺牲层被电介质代替。

2. 发明授权

US06995416B2 Memory device for storing electrical charge and method for fabricating the same 失效
标题翻译：用于存储电荷的存储器件及其制造方法
公开(公告)号：US06995416B2
公开(公告)日：2006-02-07
申请号：US10853734
申请日：2004-05-26
申请人： Hans Reisinger , Reinhard Stengl , Herbert Schäfer
发明人： Hans Reisinger , Reinhard Stengl , Herbert Schäfer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , H01L27/10814 , H01L27/10852 , H01L28/91 , H01L51/0048 , H01L51/0052 , Y10S977/842 , Y10S977/943
摘要： The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.
摘要翻译：本发明提供一种用于存储电荷的存储装置，其具有作为存储元件的施加在电极层上并连接到其上的管元件。管元件设置有电介质涂层，用于填充管元件之间的空间的填充材料。与填充材料连接的对电极形成为在电极层和对电极之间形成用于存储电荷的电容器。管元件有利地包括碳纳米管，结果由于电容器电极表面的面积急剧增加，电容器的电容。

3. 发明授权

US07947552B2 Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权
标题翻译：用掺杂法同时沉积结晶和非晶层的工艺
公开(公告)号：US07947552B2
公开(公告)日：2011-05-24
申请号：US12106667
申请日：2008-04-21
申请人： Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
发明人： Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
IPC分类号： H01L21/8238
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
摘要翻译：本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。沉积包括形成两个或更多个子层。可以为每个单独的子层改变工艺参数以优化沉积特性。

4. 发明授权

US07449389B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07449389B2
公开(公告)日：2008-11-11
申请号：US11553704
申请日：2006-10-27
申请人： Thomas Meister , Herbert Schäfer , Josef Böck , Rudolf Lachner
发明人： Thomas Meister , Herbert Schäfer , Josef Böck , Rudolf Lachner
IPC分类号： H01L21/20
CPC分类号： H01L21/8249 , H01L27/0635 , H01L27/0658 , H01L29/66242 , H01L29/7378 , H01L29/93
摘要： A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
摘要翻译：提供了一种制造半导体的方法，包括在半导体本体中限定第一分量区域和第二分量区域。通过第一分量区域形成第一外延层。第二外延层形成在第一外延层上方，包括经由第一外延层和第二外延层，与第二成分区的第二有源区独立地配置第一成分区的第一有源区的物理尺寸。在一个实施例中，第一部件是射频晶体管，第二部件是变容二极管。

5. 发明授权

US06867105B2 Bipolar transistor and method of fabricating a bipolar transistor 有权
标题翻译：双极晶体管和制造双极晶体管的方法
公开(公告)号：US06867105B2
公开(公告)日：2005-03-15
申请号：US10215152
申请日：2002-08-08
申请人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
发明人： Reinhard Stengl , Thomas Meister , Herbert Schäfer , Martin Franosch
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/7322
摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.
摘要翻译：双极晶体管包括具有集电极的第一层。第二层具有用于基座的基部切口。第三层包括用于底座的引线。第三层形成有用于发射极的发射极切口。在与基座切口相邻的第二层中形成底切。基部至少部分位于底切中。为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。中间层相对于第二层可选择性地蚀刻。至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。在与基底的接触区域中去除中间层。

6. 发明授权

US08102052B2 Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权
标题翻译：用掺杂法同时沉积结晶和非晶层的工艺
公开(公告)号：US08102052B2
公开(公告)日：2012-01-24
申请号：US13026326
申请日：2011-02-14
申请人： Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
发明人： Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
摘要翻译：本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。沉积包括形成两个或更多个子层。可以为每个单独的子层改变工艺参数以优化沉积特性。

7. 发明授权

US08003475B2 Method for fabricating a transistor structure 有权
标题翻译：晶体管结构的制造方法
公开(公告)号：US08003475B2
公开(公告)日：2011-08-23
申请号：US12051928
申请日：2008-03-20
申请人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
发明人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
摘要翻译：提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域层和在第二掩埋层上具有第二集电极宽度的第二集电极区。在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。在第一收集器区域上产生具有第二厚度的第二收集器区域。产生至少一个绝缘区域，其至少隔离收集器区域彼此。

8. 发明授权

US07968972B2 High-frequency bipolar transistor and method for the production thereof 有权
标题翻译：高频双极晶体管及其制造方法
公开(公告)号：US07968972B2
公开(公告)日：2011-06-28
申请号：US12716692
申请日：2010-03-03
申请人： Josef Böck , Thomas Meister , Reinhard Stengl , Herbert Schäfer
发明人： Josef Böck , Thomas Meister , Reinhard Stengl , Herbert Schäfer
IPC分类号： H01L29/73
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/41708 , H01L29/732
摘要： A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.
摘要翻译：高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。第一绝缘层设置在基底连接区域上。集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

9. 发明申请

US20110042046A1 INTEGRATED COOLANT CIRCUIT ARRANGEMENT, OPERATING METHOD AND PRODUCTION METHOD 有权
标题翻译：集成冷却电路布置，操作方法和生产方法
公开(公告)号：US20110042046A1
公开(公告)日：2011-02-24
申请号：US12940713
申请日：2010-11-05
申请人： Volker Lehmann , Reinhard Stengl , Herbert Schäfer
发明人： Volker Lehmann , Reinhard Stengl , Herbert Schäfer
IPC分类号： F28D15/04 , H01L21/306
CPC分类号： H01L23/473 , H01L21/30604 , H01L21/3063 , H01L23/427 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.
摘要翻译：提供一种集成电路装置及其制造方法。至少一个集成电子部件布置在基板的主要区域。该部件布置在基板中，或者通过电绝缘区域与基板隔离。主通道形成在基板上并且沿着主区域布置。每个主通道相对于纵向轴线横向地完全被基底包围。横向通道相对于主通道横向布置。每个横向通道打开至少一个主通道。超过十个横向通道进入主通道。

10. 发明授权

US07719088B2 High-frequency bipolar transistor 有权
标题翻译：高频双极晶体管
公开(公告)号：US07719088B2
公开(公告)日：2010-05-18
申请号：US11254502
申请日：2005-10-20
申请人： Josef Böck , Thomas Meister , Reinhard Stengl , Herbert Schäfer
发明人： Josef Böck , Thomas Meister , Reinhard Stengl , Herbert Schäfer
IPC分类号： H01L29/72
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/41708 , H01L29/732
摘要： A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.
摘要翻译：高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。第一绝缘层设置在基底连接区域上。集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

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