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1. 发明授权

US4481575A Arrangement in a data processing system to reduce the cycle time 失效
标题翻译：在数据处理系统中进行排列以减少周期时间
公开(公告)号：US4481575A
公开(公告)日：1984-11-06
申请号：US352663
申请日：1982-02-26
申请人： Dieter Bazlen , Johann Hajdu , Gunter Knauft
发明人： Dieter Bazlen , Johann Hajdu , Gunter Knauft
IPC分类号： G06F7/00 , G06F1/06 , G06F1/10 , G06F1/12 , G06F7/48 , G06F9/38 , G06F1/04
CPC分类号： G06F7/48 , G06F9/3869
摘要： The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking.A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains. By thus splitting the chain of logic circuits into two partial chains, the logic partial functions can be executed during that time segment which is composed of the above mentioned added time segments.
摘要翻译：数据处理系统的周期时间应该总是以这样的方式来确定，即来自源寄存器的数据在必要时被传播通过若干传输部分和线路驱动器，并且通过用于相应处理的逻辑电路链步骤，可以安全地存储在结果或接收器寄存器中，甚至在涉及的所有元素的最差情况下传播容差。因此，理想的循环时间取决于最慢链逻辑电路的处理速度，必须为最不稳定的时钟的最坏情况添加时间段。当逻辑电路链和其延迟时间被分成两部分链时，通过上述添加的时间段减少循环时间，并且如果必要，通过传输部分和线路驱动器中的传播延迟来实现具有部分延迟，并且如果宿寄存器布置在两个部分链之间。通过这样将逻辑电路链分成两部分链，逻辑部分功能可以在由上述添加的时间段组成的时间段期间执行。

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