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1. 发明授权

US06866132B2 Friction clutch with intermediate plate mounting system 有权
标题翻译：带中间板安装系统的摩擦离合器
公开(公告)号：US06866132B2
公开(公告)日：2005-03-15
申请号：US10107514
申请日：2002-03-27
申请人： Daniel V. Gochenour , Steven M. Peterson , Kevin Schlosser
发明人： Daniel V. Gochenour , Steven M. Peterson , Kevin Schlosser
IPC分类号： F16D13/38 , F16D13/50 , F16D13/69 , F16D13/71 , F16D13/56
CPC分类号： F16D13/71 , F16D13/385 , F16D13/505 , F16D2013/706
摘要： A friction clutch is provided that includes a clutch cover, an intermediate plate that is spaced apart from an engine flywheel, a first friction disk positioned between the flywheel and the intermediate plate, a pressure plate spaced apart from the intermediate plate and a second friction disk positioned between the intermediate plate and the pressure plate. The clutch further includes a first drive strap for applying a load to the intermediate plate, a second drive strap for applying a load to the pressure plate and a separator arm attached to the intermediate plate. The separator arm engages the second drive strap such that axial movement of the intermediate plate relative to the clutch cover is a fraction of the corresponding axial movement of the pressure plate during engagement and disengagement of the clutch.
摘要翻译：提供了一种摩擦离合器，其包括离合器盖，与发动机飞轮间隔开的中间板，位于飞轮和中间板之间的第一摩擦盘，与中间板间隔开的压力板和第二摩擦盘位于中间板和压板之间。离合器还包括用于向中间板施加负载的第一驱动带，用于向压板施加负载的第二驱动带和附接到中间板的分离臂。分离器臂接合第二驱动带，使得中间板相对于离合器盖的轴向运动是离合器接合和分离期间压板相应的轴向运动的一部分。

2. 发明授权

US06642749B1 Latching sense amplifier with tri-state output 失效
标题翻译：具有三态输出的锁存读出放大器
公开(公告)号：US06642749B1
公开(公告)日：2003-11-04
申请号：US10256752
申请日：2002-09-27
申请人： Sifang Wu , Steven M. Peterson , Mai T. MacLennan
发明人： Sifang Wu , Steven M. Peterson , Mai T. MacLennan
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.
摘要翻译：提供三态读出放大器，其包括使能输入，锁存器和输出驱动器。锁存器具有第一和第二互补输入以及由使能输入选通的第一和第二互补锁存器输出。输出驱动器包括数据输出，耦合到数据输出的上拉晶体管，并具有耦合到第一锁存器输出的控制端，以及耦合到数据输出的下拉晶体管，并具有耦合到第二锁存器的控制端锁存输出。

3. 发明授权

US06687183B2 Compiled variable internal self time memory 失效
标题翻译：编译变量内部自我记忆
公开(公告)号：US06687183B2
公开(公告)日：2004-02-03
申请号：US09994517
申请日：2001-11-27
申请人： Steven M. Peterson , Sifang Wu , Mai Mac Lennan , Carl A. Monzel
发明人： Steven M. Peterson , Sifang Wu , Mai Mac Lennan , Carl A. Monzel
IPC分类号： G11C800
CPC分类号： G11C7/18
摘要： A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.
摘要翻译：通过分别增加或减少存储器的内部余量（位线分离）来分别改变存储器的内部定时以允许调节存储器的访问时间更快或更慢的方法利用存储器编译器来设置数字用于驱动存储器的自身时间列的核心单元。

4. 发明授权

US06442061B1 Single channel four transistor SRAM 有权
标题翻译：单通道四晶体管SRAM
公开(公告)号：US06442061B1
公开(公告)日：2002-08-27
申请号：US09783653
申请日：2001-02-14
申请人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
发明人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/11
摘要： A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
摘要翻译：根据本发明的形成存储单元的方法。第一栅极晶体管由第一晶体管形成。第一栅极晶体管具有第一厚度的栅极氧化物。第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。第一栅极晶体管的栅极电连接到存储器单元使能线。第二栅极晶体管也由第一晶体管形成。第二栅极晶体管还具有第一厚度的栅极氧化物。第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。第二通栅晶体管的栅极电连接到存储单元使能线。第一状态节点晶体管也由第一晶体管类型形成。第一状态节点晶体管具有第二厚度的栅极氧化物。第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。第一状态节点的门电连接到第二状态节点。第二状态节点晶体管也由第一晶体管类型形成。第二状态节点晶体管也具有第二厚度的栅极氧化物。第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。第二状态节点的门电连接到第一状态节点。

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