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1. 发明授权

US06707729B2 Physically alternating sense amplifier activation 有权
标题翻译：物理交替感测放大器激活
公开(公告)号：US06707729B2
公开(公告)日：2004-03-16
申请号：US10075763
申请日：2002-02-15
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C706
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A memory device having banks of sense amplifiers with two different types of sense amplifiers is provided. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.
摘要翻译：提供了具有两个具有两种不同类型的读出放大器的读出放大器组的存储器件。用于激活第一类型的读出放大器的第一驱动器被嵌入到第一存储体中。用于激活第二类型的读出放大器的第二驱动器被嵌入到第二存储体中。在整个设备中重复在相应组内的第一和第二读出放大器驱动器的这种交替物理放置。这种交替的物理布置释放了其他功能的间隙和微型间隙，减少了用于读出放大器激活信号的总线，并允许使用大型驱动器，从而改善了读出放大器和器件本身的工作。

2. 发明授权

US06639430B2 High speed latch comparators 失效
公开(公告)号：US06639430B2
公开(公告)日：2003-10-28
申请号：US10083463
申请日：2002-02-27
申请人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
发明人： Klaas Bult , Rudy Van de Plassche , Jan Mulder
IPC分类号： G11C706
CPC分类号： H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

3. 发明授权

US06476645B1 Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit 失效
标题翻译：用于减轻绝缘体上硅（SOI）的电路中的历史效应的方法和装置
公开(公告)号：US06476645B1
公开(公告)日：2002-11-05
申请号：US09927673
申请日：2001-08-10
申请人： Philip L. Barnes
发明人： Philip L. Barnes
IPC分类号： G11C706
CPC分类号： G11C7/1087 , G11C7/065 , G11C7/1078 , H03K3/356139 , H03K3/356191
摘要： A method and apparatus for mitigating the history effect in silicon-on-insulator (SOI)-based circuitry, e.g., data interface circuitry operable as a single-ended off-chip signal receiver in a VLSI component such as a microprocessor. A sense amplifier (sense amp) latch circuit arrangement includes a sense amp operable to sense data and a latch operable to hold the sensed data. When data is available, the sense amp generates a pair of complementary data signals responsive to a control signal used for alternating the sense amp's operation between an evaluation phase and an equilibration (i.e., pre-charge) phase. A feedback circuit portion is operable to modify the control signal's logic state within a clock phase associated with one of the two complementary clocks provided to the interface circuitry. Since the equilibration phase is entered combinationally off the evaluation phase, both evaluation and equilibration can be triggered from the same clock edge.
摘要翻译：一种用于减轻绝缘体上硅（SOI）的电路中的历史效应的方法和装置，例如可用作诸如微处理器的VLSI组件中的单端片外信号接收器的数据接口电路。读出放大器（感测放大器）锁存电路装置包括可操作以感测数据的读出放大器和可操作以保持感测数据的锁存器。当数据可用时，感测放大器响应于用于在评估阶段和平衡（即，预充电）阶段之间交替感测放大器的操作的控制信号产生一对互补数据信号。反馈电路部分可操作以在与提供给接口电路的两个互补时钟之一相关联的时钟相位内修改控制信号的逻辑状态。由于平衡阶段从评估阶段组合进入，评估和平衡可以从相同的时钟边沿触发。

4. 发明授权

US06337821B1 Dynamic random access memory having continuous data line equalization except at address translation during data reading 失效
标题翻译：具有连续数据线均衡的动态随机存取存储器，除了数据读取期间的地址转换
公开(公告)号：US06337821B1
公开(公告)日：2002-01-08
申请号：US09636504
申请日：2000-08-10
申请人： Yohji Watanabe , Kenji Tsuchida
发明人： Yohji Watanabe , Kenji Tsuchida
IPC分类号： G11C706
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1048 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4094 , G11C11/4096
摘要： A data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.
摘要翻译：数据输入/输出缓冲器连接在第一数据线和第二数据线之间。均衡电路和数据锁存电路连接到第二数据线。均衡电路在正常工作期间将第二条数据线保持在复位状态。它响应于地址转换检测电路的输出暂时从复位状态释放第二数据线，从而从数据输入/输出缓冲器传送数据。数据锁存电路根据地址转换检测电路的输出锁存传送到第二数据线的数据。

5. 发明授权

US06192429B1 Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation 失效
标题翻译：具有能够在读取操作和写入操作的部分期间禁用数据输入/输出掩码（DQM）输入缓冲器的控制器的存储器件
公开(公告)号：US06192429B1
公开(公告)日：2001-02-20
申请号：US09103078
申请日：1998-06-23
申请人： Woo-seop Jeong , Yong-cheol Bae
发明人： Woo-seop Jeong , Yong-cheol Bae
IPC分类号： G11C706
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： An integrated circuit memory device includes a DQM input buffer controller that enables the DQM buffer to process the DQM mask signal during a row active period of a read operation and a write operation of an integrated circuit memory device, and during a latency period of the read operation and the write operation, and that disables the DQM buffer otherwise during the read operation and the write operation. Thus, the DQM buffer is enabled to process the DQM mask signal during those portions of the read and write operations in which the external DQM mask signal is received and the DQM buffer is otherwise disabled during the read and write operations. The controller can also disable the DQM buffer during a refresh operation of the memory device and a power-down operation of the memory device. Accordingly, reduced current consumption in the DQM buffers may be obtained by only enabling the DQM input buffers when a DQM mask signal is expected during the read and write operations of the memory device.
摘要翻译：集成电路存储器件包括DQM输入缓冲器控制器，其使DQM缓冲器能够在读操作的行活动期和集成电路存储器件的写操作期间以及在读取的等待时间期间处理DQM屏蔽信号操作和写入操作，否则在读取操作和写入操作期间禁用DQM缓冲区。因此，DQM缓冲器能够在接收外部DQM屏蔽信号的读取和写入操作的那些部分期间处理DQM屏蔽信号，并且在读取和写入操作期间禁用DQM缓冲器。控制器还可以在存储器件的刷新操作和存储器件的掉电操作期间禁用DQM缓冲器。因此，可以通过在存储器件的读取和写入操作期间期望DQM掩模信号时仅使能DQM输入缓冲器来获得DQM缓冲器中的减少的电流消耗。

6. 发明授权

US06674679B1 Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having equi-potential isolation 有权
标题翻译：用于具有等电位隔离的MRAM的多偏压点感测的可调电流模式差分放大器
公开(公告)号：US06674679B1
公开(公告)日：2004-01-06
申请号：US10262051
申请日：2002-10-01
申请人： Frederick A. Perner , Anthony P. Holden
发明人： Frederick A. Perner , Anthony P. Holden
IPC分类号： G11C706
CPC分类号： G11C7/062 , G11C11/1673 , G11C13/0033 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/77
摘要： An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier. When a second bias voltage is applied to the memory and reference cells in order to determine the memory cell value, the amplifier is able to sense slight changes in the currents or voltages associated with the selected memory cell and the reference cell and compare them to determine the state of the memory cell. This increased sensitivity enables the amplifier to have a substantially increased dynamic range without introducing components that might adversely affect the memory circuitry parameters. The memory cell array being sensed has equi-potential isolation for all unselected memory cells, thereby minimizing sneak currents through the unselected memory cells.
摘要翻译：可调电流模式差分读出放大器设置为与选定的存储单元和具有预定值的参考单元通信。放大器能够检测与所选存储单元相关联的电流和电压变化，并将其与参考单元相关的电流和电压变化进行比较。可以通过修改与施加到放大器中的选定晶体管的背栅极偏置相关的阈值电压来改变感测放大器的工作点。当将第一偏置电压施加到所选择的存储器单元以便最大化放大器的灵敏度时，该调整能力使得读出放大器的电流或电压被设置。当第二偏置电压施加到存储器和参考单元以便确定存储单元值时，放大器能够感测与所选择的存储器单元和参考单元相关联的电流或电压的轻微变化，并将其进行比较以确定存储单元的状态。这种增加的灵敏度使得放大器具有显着增加的动态范围，而不引入可能不利地影响存储器电路参数的组件。所感测的存储单元阵列对所有未选择的存储单元具有等电位隔离，从而最小化通过未选择存储单元的潜行电流。

7. 发明授权

US06597613B1 Load independent single ended sense amplifier 有权
标题翻译：负载独立单端读出放大器
公开(公告)号：US06597613B1
公开(公告)日：2003-07-22
申请号：US10113759
申请日：2002-03-27
申请人： Scott T. Becker , Betina Hold , Sudhir S. Moharir
发明人： Scott T. Becker , Betina Hold , Sudhir S. Moharir
IPC分类号： G11C706
CPC分类号： G11C7/067
摘要： A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.
摘要翻译：提供负载独立的单端读出放大器。感测放大器包括具有第一负载晶体管和第一反射电流晶体管的第一电流镜和具有第二负载晶体管和第二反射电流晶体管的第二电流镜。第一负载晶体管能够将负载电流传送到第二负载晶体管。此外，流过第一反射电流晶体管和第二反射电流晶体管的反射电流产生放大的负载电流。

8. 发明授权

US06466503B2 Semiconductor memory with current distributor 失效
标题翻译：半导体存储器与电流分配器
公开(公告)号：US06466503B2
公开(公告)日：2002-10-15
申请号：US09949652
申请日：2001-09-12
申请人： Masayuki Koizumi , Hiroyuki Shibayama
发明人： Masayuki Koizumi , Hiroyuki Shibayama
IPC分类号： G11C706
CPC分类号： G11C17/12
摘要： A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line. If it is determined that the first bit line passes the current representing the data stored in the memory cell, the partial currents from the first bit line are recombined to provide an output and one of the partial currents from the second bit line is selected to provide another output. If it is determined that the first bit line does not pass the current representing the data stored in the memory cell, i.e., the first bit line passes the current representing the data stored in the dummy cell, the partial currents from the second bit line are recombined to provide an output and one of the partial currents from the first bit line is selected to provide another output.
摘要翻译：半导体存储器配对第一和第二位线，其中一个通过表示存储在所选存储单元中的数据的电流。如果第一位线传送表示存储在存储单元中的数据的电流，则第二位线传送表示存储在虚拟单元中的数据的电流。如果第二位线传送表示存储在存储单元中的数据的电流，则第一位线传送表示存储在虚拟单元中的数据的电流。通过第一位线传输的电流被分成部分电流，并且通过第二位线传输的电流也被分为部分电流。确定表示存储在存储单元中的数据的电流是否通过第一位线。如果确定第一位线通过表示存储在存储单元中的数据的电流，则来自第一位线的部分电流被重组以提供输出，并且选择来自第二位线的部分电流中的一个以提供另一个输出。如果确定第一位线未通过表示存储在存储单元中的数据的电流，即，第一位线通过表示存储在虚拟单元中的数据的电流，则来自第二位线的部分电流为重新组合以提供输出，并且选择来自第一位线的部分电流中的一个以提供另一输出。

9. 发明授权

US06429695B1 Differential comparison circuit 有权
公开(公告)号：US06429695B1
公开(公告)日：2002-08-06
申请号：US09992335
申请日：2001-11-06
申请人： Satoru Miyabe , Yasuhiro Sugimoto
发明人： Satoru Miyabe , Yasuhiro Sugimoto
IPC分类号： G11C706
CPC分类号： H03K5/19 , H03K3/011 , H03K3/356113
摘要： A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit. Therefore, the differential comparison circuit can set the reference voltage to the differential signal and can easily obtain required accuracy.

10. 发明授权

US06377084B2 Pseudo-differential amplifiers 有权
标题翻译：伪差分放大器
公开(公告)号：US06377084B2
公开(公告)日：2002-04-23
申请号：US09255077
申请日：1999-02-22
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： G11C706
CPC分类号： H03K3/356113
摘要： Single input receivers and “pseudo differential” amplifiers can conserve scarce chip surface area and still provide fast response times in a low power CMOS environment. A first embodiment includes a single ended receiver. The single ended receiver includes a pair of cross coupled inverters. Each of the inverters includes a pair of output transmission lines. A single signal input node coupled to a source region for one of the pair of cross coupled inverters and to a current mirror such that the single ended receiver is able to convert a single ended input current received at the single signal input node into a differential input signal. A second embodiment includes a pseudo differential amplifier. The pseudo differential amplifier includes a pair of cross coupled transistors. The pseudo differential amplifier includes a pair of signal output nodes. A single signal input node is coupled to a source region for one of the transistors in the pair of cross coupled transistors and to a current mirror such that the pseudo differential amplifier is able to convert a single ended input current received at the single signal input node into a differential input signal. Methods of operation and methods of forming the single ended receivers and pseudo differential amplifiers are similarly included. The single ended receivers and pseudo differential amplifiers are fabricated in a streamlined CMOS process and provide responsive performance for single input current signal 2.0 mA and lower.
摘要翻译：单输入接收器和“伪差分”放大器可以节省很少的芯片表面积，并在低功耗CMOS环境中提供快速的响应时间。第一实施例包括单端接收器。单端接收器包括一对交叉耦合的反相器。每个逆变器包括一对输出传输线。耦合到一对交叉耦合反相器之一的源极区域和电流镜的单个信号输入节点，使得单端接收器能够将在单个信号输入节点处接收的单端输入电流转换为差分输入信号。第二实施例包括伪差分放大器。伪差分放大器包括一对交叉耦合晶体管。伪差分放大器包括一对信号输出节点。单个信号输入节点耦合到一对交叉耦合晶体管中的晶体管中的一个的源极区域和电流镜，使得伪差分放大器能够转换在单个信号输入节点处接收的单端输入电流变成差分输入信号。类似地包括操作方法和形成单端接收器和伪差分放大器的方法。单端接收器和伪差分放大器采用流线型CMOS工艺制造，并为单输入电流信号2.0 mA及更低电平提供响应性能。

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