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1. 发明授权

US07109692B1 High-speed PWM control apparatus for power converters with adaptive voltage position and its driving signal generating method 失效
标题翻译：具有自适应电压位置的电源转换器的高速PWM控制装置及其驱动信号生成方法
公开(公告)号：US07109692B1
公开(公告)日：2006-09-19
申请号：US11286321
申请日：2005-11-25
申请人： Chung-Cheng Wu , Qin Huang , Xiao-Ming Duan
发明人： Chung-Cheng Wu , Qin Huang , Xiao-Ming Duan
IPC分类号： G05F1/40
CPC分类号： H02M3/157 , H02M1/44 , H02M3/1563
摘要： A high-speed PWM control apparatus with adaptive voltage position and a driving signal generating method thereof is provided. The present invention automatically detects a change in the loading and adjusts the voltage position instantaneously for stabilizing the voltage and reducing the loading output power consumption. The present invention does not require a clock signal to generate a driving signal and does not require an error amplifier to control the modulation. Therefore, the present invention has a fast transient response that responds to the change of the loading instantaneously and has a stabilizing effect. When the apparatus is on a continuous conduction mode (CCM), the switching frequency of the controller is still fixed even though the input voltage Vin and the output voltage Vout are changed. The electrical-magnetic noise disturbance is improved.
摘要翻译：提供一种具有自适应电压位置的高速PWM控制装置及其驱动信号产生方法。本发明自动检测负载变化并且瞬时调节电压位置以稳定电压并降低负载输出功率消耗。本发明不需要时钟信号来产生驱动信号，并且不需要误差放大器来控制调制。因此，本发明具有快速瞬时响应，其瞬时响应负载变化并且具有稳定效果。当设备处于连续导通模式（CCM）时，即使输入电压Vin和输出电压Vout改变，控制器的开关频率仍然是固定的。电磁噪声干扰得到改善。

2. 发明申请

US20070024251A1 Apparatus and method for continuous conduction mode boost voltage power factor correction with an average current control mode 失效
标题翻译：具有平均电流控制模式的连续导通模式升压电压功率因数校正的装置和方法
公开(公告)号：US20070024251A1
公开(公告)日：2007-02-01
申请号：US11242915
申请日：2005-10-05
申请人： Chung-Cheng Wu , Qin Huang , Ning Zhu , Xin Zhang
发明人： Chung-Cheng Wu , Qin Huang , Ning Zhu , Xin Zhang
IPC分类号： G05F1/00
CPC分类号： G05F1/70
摘要： The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).
摘要翻译：具有本发明的平均电流控制模式的连续导通模式（CCM）升压电压功率因数校正装置使用可复位积分器来积分从电压误差放大器输出的差分电压信号和从检测获得的输入电流信号。然后将积分结果进行比较，以控制开关的占空比。因此，AC / DC电力转换器的输入电流和输入电压具有比例关系，它们的相位彼此相同。在该控制方法中使用的部件比现有技术的PFC电路简单。在一个芯片中集成更少的引脚很容易。本发明的装置具有高功率因数和低总谐波失真（THD）。

3. 发明授权

US07256569B2 Apparatus and method for continuous conduction mode boost voltage power factor correction with an average current control mode 失效
公开(公告)号：US07256569B2
公开(公告)日：2007-08-14
申请号：US11242915
申请日：2005-10-05
申请人： Chung-Cheng Wu , Qin Huang , Ning Zhu , Xin Zhang
发明人： Chung-Cheng Wu , Qin Huang , Ning Zhu , Xin Zhang
IPC分类号： G05F1/10 , G05F1/40 , H02H7/00
CPC分类号： G05F1/70
摘要： The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

4. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

5. 发明授权

US07749911B2 Method for forming an improved T-shaped gate structure 失效
标题翻译：形成改进的T形门结构的方法
公开(公告)号：US07749911B2
公开(公告)日：2010-07-06
申请号：US11001514
申请日：2004-11-30
申请人： Chung-Cheng Wu , Wen-Ting Chu
发明人： Chung-Cheng Wu , Wen-Ting Chu
IPC分类号： H01L21/311
CPC分类号： H01L21/28114 , H01L21/31116 , H01L29/42376 , H01L29/66575
摘要： A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.
摘要翻译：一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

6. 发明申请

US20090302911A1 FREQUENCY JITTER GENERATOR AND PWM CONTROLLER 失效
标题翻译：频率抖动发生器和PWM控制器
公开(公告)号：US20090302911A1
公开(公告)日：2009-12-10
申请号：US12347074
申请日：2008-12-31
申请人： Chen-Hsung Wang , Wei-Liang Kung , Chung-Cheng Wu
发明人： Chen-Hsung Wang , Wei-Liang Kung , Chung-Cheng Wu
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K3/84 , H03K4/502
摘要： A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller.
摘要翻译：提供了一种频率抖动发生器和频率抖动PWM控制器来克服传统PWM控制器通过基于输入电压改变PWM控制器的工作频率来减少电磁干扰问题的缺点，同时导致不确定性由于输入电压和负载的影响，频率抖动范围和电路设计难度大。频率抖动发生器和PWM控制器通过使用固定电压范围内的信号来调整频率抖动的范围。本发明不仅消除了输入电压和负载的影响，而且通过将频率抖动的范围固定为不大于预定百分比来简化电路设计，而不管PWM控制器的工作频率如何。

7. 发明授权

US07071515B2 Narrow width effect improvement with photoresist plug process and STI corner ion implantation 有权
标题翻译：使用光刻胶插塞工艺和STI角落离子注入的窄宽度效应改善
公开(公告)号：US07071515B2
公开(公告)日：2006-07-04
申请号：US10619114
申请日：2003-07-14
申请人： Yi-Ming Sheu , Da-Wen Lin , Cheng-Ku Chen , Po-Ying Yeh , Shi-Shung Peng , Chung-Cheng Wu
发明人： Yi-Ming Sheu , Da-Wen Lin , Cheng-Ku Chen , Po-Ying Yeh , Shi-Shung Peng , Chung-Cheng Wu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823481 , H01L21/26586 , H01L21/76237
摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.
摘要翻译：描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。去除插头并沉积绝缘体以填充沟槽。在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。在不会降低结或隔离性能的情况下实现改进。可以改变铟注入剂量和角度以提供该过程的灵活性。

8. 发明授权

US07047348B2 Method and architecture for accessing hardware devices in computer system and chipset thereof 有权
标题翻译：用于访问计算机系统及其芯片组中的硬件设备的方法和架构
公开(公告)号：US07047348B2
公开(公告)日：2006-05-16
申请号：US10128471
申请日：2002-04-22
申请人： Chung-Cheng Wu
发明人： Chung-Cheng Wu
IPC分类号： G06F13/36 , G06F13/00 , G06F13/14 , G06F13/20
CPC分类号： G06F13/4027
摘要： A method and an architecture for accessing hardware devices in a computer system and the chipset thereof are provided. A bi-directional two-wired serial interface, for instance, a system management bus (SMB), is configured to connect an I/O device, such as a local area network adapter, to a system controller such as a southbridge or a northbridge chipset. The I/O device which includes a SMB master controller serves as a SMB master device for generating a clock signal and transmitting a data signal defined by the SMB protocol to the system controller according to the clock signal. The system controller which includes a PCI master and a SMB slave controller serves as a SMB slave device for receiving commands and data bytes in the data signal from the SMB master device to drive the PCI master to access the register block of peripherals and system memory of the computer system.
摘要翻译：提供了一种用于访问计算机系统中的硬件设备及其芯片组的方法和架构。双向双向串行接口，例如系统管理总线（SMB）被配置为将诸如局域网适配器的I / O设备连接到诸如南桥或北桥的系统控制器芯片组。包括SMB主控制器的I / O设备用作用于产生时钟信号并根据时钟信号将由SMB协议定义的数据信号发送到系统控制器的SMB主设备。包括PCI主机和SMB从控制器的系统控制器用作SMB从设备，用于从SMB主设备接收数据信号中的命令和数据字节，以驱动PCI主机访问外设寄存器块和系统存储器计算机系统。

9. 发明授权

US06777280B2 Method for fabricating an integrated circuit with a transistor electrode 有权
公开(公告)号：US06777280B2
公开(公告)日：2004-08-17
申请号：US10136498
申请日：2002-04-30
申请人： Li-Chun Li , Huoy-Jong Wu , Chung-Cheng Wu , Saysamone Pittikoun , Wen-Wei Lo
发明人： Li-Chun Li , Huoy-Jong Wu , Chung-Cheng Wu , Saysamone Pittikoun , Wen-Wei Lo
IPC分类号： H01L218238
CPC分类号： H01L27/10894 , H01L21/761 , H01L21/76202 , H01L27/10897
摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

10. 发明授权

US5633520A Neuron MOSFET with different interpolysilicon oxide 失效
标题翻译：具有不同的多晶硅氧化物的神经元MOSFET
公开(公告)号：US5633520A
公开(公告)日：1997-05-27
申请号：US667609
申请日：1996-06-21
申请人： Chung-Cheng Wu , Ming-Tzong Yang
发明人： Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/822 , H01L27/115 , H01L27/108 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , H01L21/8221 , H01L29/788 , Y10S148/116 , Y10S148/117 , Y10S148/163 , Y10S438/981
摘要： An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
摘要翻译：制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

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