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1. 发明授权

US5633520A Neuron MOSFET with different interpolysilicon oxide 失效
标题翻译：具有不同的多晶硅氧化物的神经元MOSFET
公开(公告)号：US5633520A
公开(公告)日：1997-05-27
申请号：US667609
申请日：1996-06-21
申请人： Chung-Cheng Wu , Ming-Tzong Yang
发明人： Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/822 , H01L27/115 , H01L27/108 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , H01L21/8221 , H01L29/788 , Y10S148/116 , Y10S148/117 , Y10S148/163 , Y10S438/981
摘要： An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
摘要翻译：制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

2. 发明授权

US5650346A Method of forming MOSFET devices with buried bitline capacitors 失效
标题翻译：用掩埋位线电容器形成MOSFET器件的方法
公开(公告)号：US5650346A
公开(公告)日：1997-07-22
申请号：US557546
申请日：1995-11-14
申请人： Hong-Tsz Pan , Chung-Cheng Wu , Ming-Tzong Yang
发明人： Hong-Tsz Pan , Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/11558
摘要： A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:forming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.
摘要翻译：一种MOSFET器件，其具有覆盖有介电材料的衬底，该器件包括电容耦合到多晶硅电极的多个掩埋导体，其通过以下方式制成：在包含MOSFET器件的区域之间形成通过离子注入穿过衬底中的多个位线的区域栅极氧化物以预定图案进入衬底，并且在电介质材料上形成跨越位线的多晶硅电极。

3. 发明授权

US5554545A Method of forming neuron mosfet with different interpolysilicon oxide thickness 失效
标题翻译：形成具有不同的多晶硅氧化物厚度的神经元mosfet的方法
公开(公告)号：US5554545A
公开(公告)日：1996-09-10
申请号：US299266
申请日：1994-09-01
申请人： Chung-Cheng Wu , Ming-Tzong Yang
发明人： Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/822 , H01L27/115 , H01L21/265
CPC分类号： H01L27/115 , H01L21/8221 , H01L29/788 , Y10S148/116 , Y10S148/117 , Y10S148/163 , Y10S438/981
摘要： An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.
摘要翻译：制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

4. 发明授权

US5436190A Method for fabricating semiconductor device isolation using double oxide spacers 失效
标题翻译：使用双氧化物间隔物制造半导体器件隔离的方法
公开(公告)号：US5436190A
公开(公告)日：1995-07-25
申请号：US344007
申请日：1994-11-23
申请人： Ming-Tzong Yang , Chung-Cheng Wu
发明人： Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： H01L21/763 , H01L21/76
CPC分类号： H01L21/763
摘要： A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the oxide encroachment into the device area associated with LOCOS techniques, thereby increasing device density. The method involves etching trenches, less than one half micrometer in width in the silicon substrate and forming sidewall spacer in the trench. The trench is filled with doped polysilicon and planarized, forming a trench which is planar with the device region. These isolation trenches are made in both N and P-wells for fabricating CMOS circuits having ULSI densities.
摘要翻译：实现了用于在用于隔离各个场效应晶体管（FET）的半导体衬底中制造非常窄的电隔离沟槽的方法。该方法消除了与LOCOS技术相关的器件区域的氧化物侵蚀，从而增加器件密度。该方法包括蚀刻在硅衬底中宽度小于半微米的沟槽，并在沟槽中形成侧壁间隔物。沟槽填充有掺杂的多晶硅并且被平坦化，形成与器件区域平坦的沟槽。这些隔离沟槽在N阱和P阱中制造，用于制造具有ULSI密度的CMOS电路。

5. 发明授权

US5350700A Method of fabricating bipolar transistors with buried collector region 失效
标题翻译：制造具有埋地集电极区域的双极晶体管的方法
公开(公告)号：US5350700A
公开(公告)日：1994-09-27
申请号：US160243
申请日：1993-12-02
申请人： Ming-Tzong Yang , Chung-Cheng Wu
发明人： Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： H01L21/331 , H01L21/74 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/74
摘要： A method of fabricating a bipolar transistor with a buried subcollector by forming a collector layer and a base layer in a semiconductor substrate. A polysilicon layer is deposited over the base layer and spaced emitter and base contact regions formed in the base layer. A mask is formed over the emitter and base contact regions and the substrate anisotropically etched to form pedestals with vertical sidewalls. A masking layer is formed on the vertical sidewalls, and a large angle ion implant used to introduce ions beneath the collector layer, thereby forming a subcollector region.
摘要翻译：一种通过在半导体衬底中形成集电极层和基极层来制造具有掩埋子集电极的双极晶体管的方法。在基底层上沉积多晶硅层，并且在基底层中形成间隔开的发射极和基极接触区域。在发射极和基极接触区域上形成掩模，并且各向异性蚀刻衬底以形成具有垂直侧壁的基座。掩模层形成在垂直侧壁上，并且大角度离子注入用于将离子引入集电极层下面，从而形成子集电极区域。

6. 发明授权

US5895945A Single polysilicon neuron MOSFET 失效
标题翻译：单多晶硅神经元MOSFET
公开(公告)号：US5895945A
公开(公告)日：1999-04-20
申请号：US791596
申请日：1997-01-31
申请人： Hong-Tsz Pan , Chung-Cheng Wu , Ming-Tzong Yang
发明人： Hong-Tsz Pan , Chung-Cheng Wu , Ming-Tzong Yang
IPC分类号： H01L21/8247 , H01L27/108
CPC分类号： H01L27/11521 , H01L27/11558
摘要： A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.
摘要翻译：一种具有被绝缘材料覆盖的衬底的MOSFET器件，该器件包括电容耦合到多晶硅电极的多个掩埋导体，所述多个掩埋导体通过以下步骤形成，所述步骤包括：在包含MOSFET器件的区域之间形成具有衬底中的多个位线的区域，以预定图案将栅极氧化物注入到衬底中，并且在穿过位线的电介质材料上形成多晶硅电极。

7. 发明授权

US5541876A Memory cell fabricated by floating gate structure 失效
标题翻译：通过浮栅结构制造的存储单元
公开(公告)号：US5541876A
公开(公告)日：1996-07-30
申请号：US251972
申请日：1994-06-01
申请人： Chen-Chin Hsue , Ming-Tzong Yang , Chung-Cheng Wu
发明人： Chen-Chin Hsue , Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： G11C17/12 , H01L27/112 , G11C11/34
CPC分类号： G11C17/12 , H01L27/112
摘要： A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.
摘要翻译：公开了一种存储单元及其制造方法。对于选择为“关闭”的单元，ROM码不会植入浮动门。该存储单元具有比常规电池低得多的阈值电压，并且避免了注入诱导的晶体损伤。

8. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

9. 发明授权

US07749911B2 Method for forming an improved T-shaped gate structure 失效
标题翻译：形成改进的T形门结构的方法
公开(公告)号：US07749911B2
公开(公告)日：2010-07-06
申请号：US11001514
申请日：2004-11-30
申请人： Chung-Cheng Wu , Wen-Ting Chu
发明人： Chung-Cheng Wu , Wen-Ting Chu
IPC分类号： H01L21/311
CPC分类号： H01L21/28114 , H01L21/31116 , H01L29/42376 , H01L29/66575
摘要： A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.
摘要翻译：一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

10. 发明申请

US20090302911A1 FREQUENCY JITTER GENERATOR AND PWM CONTROLLER 失效
标题翻译：频率抖动发生器和PWM控制器
公开(公告)号：US20090302911A1
公开(公告)日：2009-12-10
申请号：US12347074
申请日：2008-12-31
申请人： Chen-Hsung Wang , Wei-Liang Kung , Chung-Cheng Wu
发明人： Chen-Hsung Wang , Wei-Liang Kung , Chung-Cheng Wu
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K3/84 , H03K4/502
摘要： A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller.
摘要翻译：提供了一种频率抖动发生器和频率抖动PWM控制器来克服传统PWM控制器通过基于输入电压改变PWM控制器的工作频率来减少电磁干扰问题的缺点，同时导致不确定性由于输入电压和负载的影响，频率抖动范围和电路设计难度大。频率抖动发生器和PWM控制器通过使用固定电压范围内的信号来调整频率抖动的范围。本发明不仅消除了输入电压和负载的影响，而且通过将频率抖动的范围固定为不大于预定百分比来简化电路设计，而不管PWM控制器的工作频率如何。

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