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1. 发明申请

US20090294959A1 Semiconductor package device, semiconductor package structure, and fabrication methods thereof 有权
标题翻译：半导体封装器件，半导体封装结构及其制造方法
公开(公告)号：US20090294959A1
公开(公告)日：2009-12-03
申请号：US12315787
申请日：2008-12-04
申请人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
发明人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
IPC分类号： H01L23/522 , H01L23/532 , H01L23/28 , H01L23/31
CPC分类号： H01L23/4334 , H01L21/486 , H01L23/31 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/00 , H01L2224/81
摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要翻译：提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料碰撞，切割晶片难度大。

2. 发明申请

US20090057799A1 Sensor semiconductor device and method for fabricating the same 审中-公开
标题翻译：传感器半导体器件及其制造方法
公开(公告)号：US20090057799A1
公开(公告)日：2009-03-05
申请号：US12229651
申请日：2008-08-26
申请人： Chang-Yueh Chan , Chih-Ming Huang , Chien-Ping Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
发明人： Chang-Yueh Chan , Chih-Ming Huang , Chien-Ping Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L31/0203 , H01L31/02164 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant.
摘要翻译：提供一种传感器半导体器件及其制造方法。至少一个传感器芯片被安装并电连接到引线框架。依次执行第一和第二封装成型工艺以形成用于封装传感器芯片和引线框架的一部分的透明密封剂，并形成用于封装透明密封剂的不透光密封剂。透明密封剂具有形成在对应于传感器芯片的传感器区域上方的位置处的透光部分。透光部分从不透光的密封剂暴露出来。光可以穿透透光部分，而不使用附加的盖板，从而减少制造步骤和成本。上述布置避免了由多孔密封剂引起的可靠性差的现有技术问题，以及由仅通过透明密封剂封装的传统芯片的环境光的干扰引起的差信号接收。

3. 发明申请

US20080283982A1 Multi-chip semiconductor device having leads and method for fabricating the same 审中-公开
标题翻译：具有引线的多芯片半导体器件及其制造方法
公开(公告)号：US20080283982A1
公开(公告)日：2008-11-20
申请号：US12152802
申请日：2008-05-15
申请人： Chung-Lun Liu , Chin-Huang Chang , Chien-Ping Huang , Chang-Yueh Chan , Chih-Ming Huang
发明人： Chung-Lun Liu , Chin-Huang Chang , Chien-Ping Huang , Chang-Yueh Chan , Chih-Ming Huang
IPC分类号： H01L21/58 , H01L23/495
CPC分类号： H05K1/141 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/49861 , H01L24/48 , H01L24/81 , H01L24/85 , H01L24/97 , H01L25/0655 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H05K3/3421 , H05K3/3436 , H05K2201/1034 , H05K2201/10659 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads. By the multi-chip semiconductor device and the method for fabricating the same as proposed in the present invention, problems like poor reliability caused by stress induced by several types of materials in a semiconductor package into which a substrate and leads are integrated, moisture absorption by an encapsulated substrate, and cracks developed as a result of moisture absorption by the substrate can be avoided.
摘要翻译：本发明提出一种具有引线的多芯片半导体器件及其制造方法。该方法包括以下步骤：提供具有设置在其表面上的多个连接焊盘的基板; 将多个半导体芯片安装在所述基板的表面上，并且将所述半导体芯片电连接到所述基板的表面; 在衬底上形成密封剂以封装半导体芯片并暴露连接焊盘以形成封装单元; 并且提供具有多个引线的引线框架，并且将从封装单元暴露的连接焊盘电连接到引线框架的引线以形成具有引线的多芯片半导体器件，从而形成具有引线的多芯片半导体器件。通过本发明中提出的多芯片半导体器件及其制造方法，由半导体封装中由几种材料引起的应力引起的可靠性差的问题，其中衬底和引线被集成到其中，由于可以避免被封装的基材和由于基材吸湿而显影的裂纹。

4. 发明授权

US08304891B2 Semiconductor package device, semiconductor package structure, and fabrication methods thereof 有权
标题翻译：半导体封装器件，半导体封装结构及其制造方法
公开(公告)号：US08304891B2
公开(公告)日：2012-11-06
申请号：US12315787
申请日：2008-12-04
申请人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
发明人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
IPC分类号： H01L23/28 , H01L23/31 , H01L23/52 , H01L23/00
CPC分类号： H01L23/4334 , H01L21/486 , H01L23/31 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/00 , H01L2224/81
摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要翻译：提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料碰撞，切割晶片难度大。

5. 发明申请

US20080230913A1 Stackable semiconductor device and fabrication method thereof 审中-公开
标题翻译：可堆叠半导体器件及其制造方法
公开(公告)号：US20080230913A1
公开(公告)日：2008-09-25
申请号：US12077223
申请日：2008-03-18
申请人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Chun-Chi Ke
发明人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Chun-Chi Ke
IPC分类号： H01L23/488 , H01L21/304
CPC分类号： H01L21/78 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/05001 , H01L2224/05147 , H01L2224/05155 , H01L2224/05611 , H01L2224/1147 , H01L2224/1184 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/2518 , H01L2224/48091 , H01L2224/48227 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/13099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices. Thereby, the first and second metal layers formed on the active surface and the non-active surface of the semiconductor device can be stacked and connected to constitute a multi-die stack structure, thereby increasing integration without increasing the area of the stacked dies. Further, the problems known in the prior art of poor electrical connection, complicated manufacturing process and increased cost as a result of using wire bonding and TSV can be avoided.
摘要翻译：本发明提供了一种可堆叠半导体器件及其制造方法，包括提供具有安装在其上的多个管芯的晶片，晶粒和晶片两者分别具有相互相对的有源表面和非有效表面，其中每个管芯具有形成在其有效表面上的多个焊盘和形成在相邻焊盘之间的槽，以在其中形成电连接到焊盘的第一金属层; 随后使所述晶片的非活性表面变薄到所述凹槽所在的位置以暴露出所述第一金属层，以及在所述晶片的非活性表面上形成用于与所述第一金属层电连接的第二金属层; 以及分离所述管芯以形成多个可堆叠的半导体器件。由此，形成在半导体器件的有源表面和非有源表面上的第一和第二金属层可以被堆叠和连接以构成多管芯堆叠结构，从而增加集成度而不增加堆叠管芯的面积。此外，可以避免由于使用引线接合和TSV而导致的不良电连接，复杂的制造工艺和增加的成本的现有技术中已知的问题。

6. 发明申请

US20080283971A1 Semiconductor Device and Its Fabrication Method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080283971A1
公开(公告)日：2008-11-20
申请号：US12102213
申请日：2008-04-14
申请人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang
发明人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang
IPC分类号： H01L23/488 , H01L21/304
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/27 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2224/274 , H01L2224/48091 , H01L2224/97 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15184 , H01L2924/15311 , H01L2924/15331 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device and a fabrication method thereof are disclosed. The method includes attaching a wafer with a plurality of chips on a carrier board having an insulating layer, a plurality of conductive circuits and a bottom board; forming a plurality of first grooves between solder pads of adjacent chips to expose the conductive circuits, and filling the first grooves with an insulating adhesive layer; forming second grooves in the insulating adhesive layer; and cutting among the chips to separate the chips from one another.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括在具有绝缘层，多个导电电路和底板的载体板上附着具有多个芯片的晶片; 在相邻芯片的焊盘之间形成多个第一凹槽以暴露导电电路，并用绝缘粘合剂层填充第一凹槽; 在所述绝缘粘合剂层中形成第二槽; 并在芯片之间切割以将芯片彼此分离。

7. 发明申请

US20080258306A1 Semiconductor Device and Method for Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080258306A1
公开(公告)日：2008-10-23
申请号：US12105538
申请日：2008-04-18
申请人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
发明人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02371 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/48091 , H01L2224/82001 , H01L2224/97 , H01L2225/06562 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2224/82 , H01L2924/01028 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。

8. 发明申请

US20080251937A1 Stackable semiconductor device and manufacturing method thereof 审中-公开
标题翻译：可堆叠半导体器件及其制造方法
公开(公告)号：US20080251937A1
公开(公告)日：2008-10-16
申请号：US12082724
申请日：2008-04-11
申请人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L21/76898 , H01L25/0657 , H01L2224/48091 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2924/00014
摘要： A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided.
摘要翻译：公开了一种可堆叠半导体器件及其制造方法。该方法包括提供由多个芯片组成的晶片，其中在每个芯片的有源表面上形成多个焊盘，并且在任何两个相邻芯片的焊盘之间形成多个沟槽; 在任何两个相邻芯片的焊盘之间的区域上形成电介质层; 在与所述焊料焊盘电连接的所述电介质层上形成金属层，并在所述金属层上形成连接层，其中所述连接层的宽度小于所述金属层的宽度; 沿着凹槽切割以破坏相邻芯片之间的电连接; 使晶片的非活性表面变薄至金属层从晶片露出的程度; 并分离所述芯片以形成多个可堆叠半导体器件。因此，通过半导体器件的连接层与另一半导体器件的金属层之间的电连接层叠并电连接多个半导体器件，可以获得多芯片堆叠结构，从而有效地集成更多的芯片，而不必增加堆积面积，进一步避免了现有技术中已知的电连接不良，制造工艺复杂，成本高的问题。

9. 发明申请

US20090261476A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090261476A1
公开(公告)日：2009-10-22
申请号：US12148319
申请日：2008-04-18
申请人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
发明人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
IPC分类号： H01L23/482 , H01L21/60
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/82001 , H01L2225/1035 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。

10. 发明申请

US20090039527A1 Sensor-type package and method for fabricating the same 审中-公开
标题翻译：传感器型封装及其制造方法
公开(公告)号：US20090039527A1
公开(公告)日：2009-02-12
申请号：US12221725
申请日：2008-08-06
申请人： Chang-Yueh Chan , Chien-Ping Huang , Tse-Wen Chang , Chin-Huang Chang , Chih-Ming Huang
发明人： Chang-Yueh Chan , Chien-Ping Huang , Tse-Wen Chang , Chin-Huang Chang , Chih-Ming Huang
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L2224/05001 , H01L2224/056 , H01L2224/13 , H01L2224/13025 , H01L2224/16146 , H01L2224/94 , H01L2224/97 , H01L2924/19104 , H01L2924/19105 , H01L2924/00014 , H01L2224/81 , H01L2224/83
摘要： A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and a plurality of bond pads connected to the metallic pillars form through silicon vias (TSVs). A groove is formed on a second surface of each of the semiconductor chips to expose the metallic pillars. A plurality of sensor chips having TSVs are stacked in the grooves of the semiconductor chips and electrically connected to the exposed metallic pillars. A transparent cover is mounted onto the second surfaces of the semiconductor chips to cover the grooves. A plurality of conductive components are implanted on the bond pads of the semiconductor chips. The wafer is cut along borders among the semiconductor chips.
摘要翻译：提供了一种传感器型封装及其制造方法。提供具有多个半导体芯片的晶片，其中在每个半导体芯片的第一表面上形成多个孔，并且形成在孔中的多个金属柱和连接到金属柱的多个接合焊盘通过硅通孔（TSV）形成。在每个半导体芯片的第二表面上形成凹槽以暴露金属柱。具有TSV的多个传感器芯片堆叠在半导体芯片的凹槽中并电连接到暴露的金属柱。透明盖安装在半导体芯片的第二表面上以覆盖凹槽。在半导体芯片的接合焊盘上注入多个导电元件。在半导体芯片之间沿着边缘切割晶片。

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