专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100255635A1 FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20100255635A1
公开(公告)日：2010-10-07
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

2. 发明授权

US07768106B2 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US07768106B2
公开(公告)日：2010-08-03
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Ping Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Ping Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

3. 发明申请

US20080224289A1 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

4. 发明授权

US07266888B2 Method for fabricating a warpage-preventive circuit board 有权
标题翻译：防翘曲电路板的制造方法
公开(公告)号：US07266888B2
公开(公告)日：2007-09-11
申请号：US11043496
申请日：2005-01-25
申请人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
发明人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H01L23/49822 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H05K1/0271 , H05K3/28 , H05K2201/09663 , H05K2201/09781 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916 , H01L2224/05599 , H01L2924/00012
摘要： A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要翻译：提供了一种制造防翘曲电路板的方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电绝缘性电路板的表面上，绝缘芯层在没有导电迹线的区域处，其中相邻的虚拟电路区域至少间隔开。在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服并且可以提高制造的半导体器件的可靠性。

5. 发明授权

US07655503B2 Method for fabricating semiconductor package with stacked chips 有权
标题翻译：制造具有堆叠芯片的半导体封装的方法
公开(公告)号：US07655503B2
公开(公告)日：2010-02-02
申请号：US11649144
申请日：2007-01-02
申请人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
发明人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
IPC分类号： H01L21/50
CPC分类号： H01L23/49575 , H01L23/3135 , H01L23/49531 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/4911 , H01L2924/00014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
摘要翻译：提出了一种具有堆叠芯片的半导体封装及其制造方法。半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。

6. 发明申请

US20090014860A1 Multi-chip stack structure and fabricating method thereof 审中-公开
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20090014860A1
公开(公告)日：2009-01-15
申请号：US12011832
申请日：2008-01-29
申请人： Chung-Lun Liu , Jung-Pin Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Chung-Lun Liu , Jung-Pin Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L25/0652 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2924/00012
摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖，并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。

7. 发明申请

US20080176358A1 Fabrication method of multichip stacking structure 审中-公开
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20080176358A1
公开(公告)日：2008-07-24
申请号：US12009866
申请日：2008-01-23
申请人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
发明人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
IPC分类号： H01L21/56
CPC分类号： H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/4945 , H01L2224/73265 , H01L2224/83136 , H01L2224/83191 , H01L2224/838 , H01L2224/92247 , H01L2225/0651 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/07802 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a fabrication method of a multi-chip stacking structure. The method includes steps of: stacking the first chips on the chip carrier in a step-like manner to form a first chip module; electrically connecting the first chip module to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module in step-like manner to form a second chip module, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer with the bottom chip deviated from the top chip horizontally in a direction toward the first bonding wires; and electrically connecting the bond pads of the second chip module to the chip carrier by a plurality of second bonding wires.
摘要翻译：本发明提供一种多芯片堆叠结构的制造方法。该方法包括以下步骤：以阶梯状方式堆叠芯片载体上的第一芯片以形成第一芯片模块; 通过多个第一接合线将第一芯片模块电连接到芯片载体; 在第一芯片模块上堆叠第二芯片以形成第二芯片模块，其中第二芯片模块的底部芯片通过粘合剂层堆叠在第一芯片模块的顶部芯片上，底部芯片偏离从顶部芯片沿着朝向第一接合线的方向水平地; 以及通过多个第二接合线将所述第二芯片模块的所述接合焊盘电连接到所述芯片载体。

8. 发明申请

US20060022315A1 Semiconductor package with stacked chips and method for fabricating the same 有权
标题翻译：具有堆叠芯片的半导体封装及其制造方法
公开(公告)号：US20060022315A1
公开(公告)日：2006-02-02
申请号：US10982559
申请日：2004-11-05
申请人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
发明人： Jung-Pin Huang , Chin-Huang Chang , Chung-Lun Liu
IPC分类号： H01L21/50
CPC分类号： H01L23/49575 , H01L23/3135 , H01L23/49531 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/4911 , H01L2924/00014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
摘要翻译：提出了一种具有堆叠芯片的半导体封装及其制造方法。半导体封装包括具有多个引线和支撑延伸部的引线框架; 至少一个具有活性表面的预制包装和连接到引线框架的支撑延伸部的非活性表面; 至少一个芯片安装在所述预制包装的有效表面上; 用于将引线框架，预成型封装和芯片电连接的多个接合线; 以及用于封装预制包装，芯片，接合线和引线框架的一部分的密封剂。预制包装的活性表面用于承载芯片，并且可以用作跳线，以便解决多芯片模块的已知的良好的裸片（KGD）问题。

9. 发明申请

US20050145413A1 Method for fabricating a warpage-preventive circuit board 有权
标题翻译：防翘曲电路板的制造方法
公开(公告)号：US20050145413A1
公开(公告)日：2005-07-07
申请号：US11043496
申请日：2005-01-25
申请人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
发明人： Chin-Huang Chang , Chin-Tien Chiu , Chung-Lun Liu
IPC分类号： H01L23/498 , H05K1/02 , H05K3/28 , H05K1/03 , H05K1/00 , H05K3/02
CPC分类号： H01L23/49822 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H05K1/0271 , H05K3/28 , H05K2201/09663 , H05K2201/09781 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916 , H01L2224/05599 , H01L2924/00012
摘要： A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.
摘要翻译：提供了一种防翘曲电路板及其制造方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电气绝缘电路板的表面上 - 绝缘芯层在没有导电迹线的区域处，其中相邻的虚设电路区域至少间隔开。在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服并且可以提高制造的半导体器件的可靠性。

10. 发明申请

US20050006785A1 Manufacturing method for multichip module 审中-公开
标题翻译：多芯片模块的制造方法
公开(公告)号：US20050006785A1
公开(公告)日：2005-01-13
申请号：US10913977
申请日：2004-08-05
申请人： Chung-Lun Liu , Chin-Huang Chang
发明人： Chung-Lun Liu , Chin-Huang Chang
IPC分类号： H01L25/065 , H01L35/24
CPC分类号： H01L23/02 , H01L24/29 , H01L24/33 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29324 , H01L2224/29347 , H01L2224/29386 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/83138 , H01L2224/83192 , H01L2224/838 , H01L2224/92247 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2924/01007 , H01L2924/01074 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/05032 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： A manufacturing method for a multi-chip module is provided, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. An adhesive with fillers allows a second chip to be superimposed over a first chip after the first chip is electrically connected to the chip carrier. The diameter of the fillers is higher than loop height of the bonding wires that are positioned above the active surface of the first chip to prevent the bonding wires to come in contact with the second chip. Moreover, the other embodiment of the fillers (such as copper or aluminum) with high thermal conductivity is also capable of enhancing heat dissipation of the stacked package application.
摘要翻译：提供了一种用于多芯片模块的制造方法，其被设计成在单个封装中以堆叠的方式在芯片载体上包装两个或更多个半导体芯片。具有填料的粘合剂允许在第一芯片电连接到芯片载体之后将第二芯片叠加在第一芯片上。填料的直径高于位于第一芯片的有效表面上方的接合线的环路高度，以防止接合线与第二芯片接触。此外，具有高导热性的填料（例如铜或铝）的另一个实施方案也能够增强层叠包装应用的散热。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式