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1. 发明授权

US08873244B2 Package structure 有权
标题翻译：包装结构
公开(公告)号：US08873244B2
公开(公告)日：2014-10-28
申请号：US12759117
申请日：2010-04-13
申请人： Pang-Chun Lin , Hsiao-Jen Hung , Chun-Yuan Li , Chien-Ping Huang , Chun-Chi Ke
发明人： Pang-Chun Lin , Hsiao-Jen Hung , Chun-Yuan Li , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10 , H01L23/498 , H01L25/10 , H01L23/31 , H01L23/00
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49861 , H01L24/16 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3025 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/49146 , Y10T29/49165 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.
摘要翻译：封装结构包括具有第一密封剂和嵌入第一密封剂并暴露于第一密封剂的布线层的基体。布线层具有多个导电迹线和多个第一电接触焊盘。第一密封剂具有用于暴露第一电接触焊盘的开口，与布线层电连接的芯片，以及形成在基体上的用于覆盖芯片和布线层的第二密封剂，从而提供均匀的表面，以防止密封剂芯片安装时开裂。

2. 发明授权

US08304268B2 Fabrication method of semiconductor package structure 有权
标题翻译：半导体封装结构的制造方法
公开(公告)号：US08304268B2
公开(公告)日：2012-11-06
申请号：US12770059
申请日：2010-04-29
申请人： Pang-Chun Lin , Chun-Yuan Li , Chien-Ping Huang , Chun-Chi Ke
发明人： Pang-Chun Lin , Chun-Yuan Li , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H01L21/44
CPC分类号： H01L23/495 , H01L21/4832 , H01L23/3107 , H01L23/4951 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/181 , Y10T29/49117 , Y10T29/49171 , Y10T29/49172 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.
摘要翻译：半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

3. 发明授权

US08154115B1 Package structure having MEMS element and fabrication method thereof 有权
标题翻译：具有MEMS元件的封装结构及其制造方法
公开(公告)号：US08154115B1
公开(公告)日：2012-04-10
申请号：US13024672
申请日：2011-02-10
申请人： Chang-Yueh Chan , Chien-Ping Huang , Chun-Chi Ke , Shih-Kuang Chiu
发明人： Chang-Yueh Chan , Chien-Ping Huang , Chun-Chi Ke , Shih-Kuang Chiu
IPC分类号： H01L23/12
CPC分类号： B81B7/007 , B81C2203/0154 , H01L2224/48091 , H01L2924/1461 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A package structure having an MEMS element includes: a chip having at least an MEMS element and a plurality of first conductive pads; a lid disposed on the chip to cover the MEMS element and having a plurality of second conductive pads formed thereon; a plurality of bonding wires electrically connecting the first and second conductive pads; a plurality of first bumps disposed on the second conductive pads, respectively; an encapsulant formed on the chip to encapsulate the lid, the bonding wires, the first and second conductive pads and the first bumps while exposing the top surfaces of the first bumps; and a plurality of circuits formed on the encapsulant and electrically connecting to the exposed first bumps, thereby avoiding the conventional drawback of electrical connection failure caused by position deviation of bonding wires due to mold flow of the encapsulant.
摘要翻译：具有MEMS元件的封装结构包括：具有至少MEMS元件和多个第一导电焊盘的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有形成在其上的多个第二导电焊盘的盖; 电连接第一和第二导电焊盘的多个接合线; 分别设置在第二导电焊盘上的多个第一凸块; 密封剂，形成在所述芯片上以封装所述盖，所述接合线，所述第一和第二导电焊盘和所述第一凸起，同时暴露所述第一凸块的顶表面; 以及形成在密封剂上并与露出的第一凸起电连接的多个电路，从而避免了由于密封剂的模具流动导致的接合线的位置偏移导致的电连接故障的常规缺点。

4. 发明申请

US20120013006A1 CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：芯片尺寸包装及其制造方法
公开(公告)号：US20120013006A1
公开(公告)日：2012-01-19
申请号：US12955613
申请日：2010-11-29
申请人： Chiang-Cheng Chang , Chien-Ping Huang , Chun-Chi Ke
发明人： Chiang-Cheng Chang , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H01L23/485 , H01L21/786
CPC分类号： H01L21/561 , H01L23/3121 , H01L24/19 , H01L24/96 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/96 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.
摘要翻译：提供了一种芯片级封装的制造方法，其包括在芯片的有源表面上形成保护层并将芯片的非活性表面固定到透明载体上; 进行成型工序; 从芯片上除去保护层并执行再分配层（RDL）工艺，从而解决了将芯片直接附着在粘合膜上所引起的常规问题，例如由热引起的膜软化，密封剂溢出，翘曲，芯片偏差和污染导致在RDL工艺中形成的布线层与芯片电极焊盘之间的电连接不良，甚至结果导致废品。此外，本发明中使用的透明载体可以通过激光分离并在该过程中重复使用以帮助降低制造成本。

5. 发明申请

US20110198737A1 QUAD FLAT NON-LEADED PACKAGE STRUCTURE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING FUNCTION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有电磁干扰屏蔽功能的四边形非线性封装结构及其制造方法
公开(公告)号：US20110198737A1
公开(公告)日：2011-08-18
申请号：US12769024
申请日：2010-04-28
申请人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
发明人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H01L23/552 , H01L21/60
CPC分类号： H01L24/96 , H01L21/561 , H01L23/3107 , H01L23/49548 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.
摘要翻译：提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。进一步提出如上所述的制造封装结构的方法。

6. 发明申请

US20110177643A1 FABRICATION METHOD OF PACKAGE STRUCTURE HAVING MEMS ELEMENT 有权
标题翻译：具有MEMS元件的封装结构的制造方法
公开(公告)号：US20110177643A1
公开(公告)日：2011-07-21
申请号：US12769087
申请日：2010-04-28
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
IPC分类号： H01L21/56 , H01L21/60
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
摘要翻译：提供具有至少MEMS元件的封装结构的制造方法，包括：制备具有电连接焊盘和所述至少MEMS元件的晶片; 设置用于覆盖所述至少一个MEMS元件的盖，所述盖具有在其上形成的金属层; 电连接焊盘和金属层与接合线; 形成用于覆盖盖子，接合线，电连接垫和金属层的密封剂; 去除所述密封剂的部分以将所述接合线分别分离成第一和第二子接合线，其中所述第一和第二次接合线的顶端被暴露，所述第一子接合线电连接到所述电连接焊盘，以及所述第二子接合线电连接到所述金属层; 在所述密封剂上形成用于电连接到所述第一子接合线的金属迹线; 在金属痕迹上形成凸块; 并执行单独处理。

7. 发明申请

US20110175210A1 EMI SHIELDING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译： EMI屏蔽包装结构及其制造方法
公开(公告)号：US20110175210A1
公开(公告)日：2011-07-21
申请号：US12769053
申请日：2010-04-28
申请人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
发明人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L23/552 , H01L21/561 , H01L21/78 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L24/96 , H01L24/97 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.
摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片，在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。进一步提供通过两个切割工艺的上述结构的制造方法。第一切割工艺通过切割密封剂形成凹槽。在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

8. 发明申请

US20110175179A1 PACKAGE STRUCTURE HAVING MEMS ELEMENT 有权
标题翻译：具有MEMS元件的封装结构
公开(公告)号：US20110175179A1
公开(公告)日：2011-07-21
申请号：US12769993
申请日：2010-04-29
申请人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
发明人： Chi-Hsin Chiu , Chih-Ming Huang , Chang-Yueh Chan , Hsin-Yi Liao , Chun-Chi Ke
IPC分类号： H01L29/84 , H01L23/52
CPC分类号： B81B7/0064 , B81B7/007 , B81B2207/095 , H01L21/56 , H01L23/315 , H01L23/552 , H01L24/48 , H01L2224/48227 , H01L2224/48465 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/1461 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
摘要翻译：提供具有至少MEMS元件的封装结构，其包括具有电连接焊盘和MEMS元件的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有设置在其上的金属层的盖; 电连接到电连接焊盘的第一子接合线; 电连接到金属层的第二子接合线; 设置在所述芯片上的密封剂，其中所述第一和第二子接合线的顶端从所述密封剂露出; 以及设置在密封剂上并电连接到第一子接合线的金属迹线。封装结构有利地具有减小的尺寸，相对低的成本，不同的凸起位置和增强的EMI屏蔽效果。

9. 发明申请

US20100297842A1 CONDUCTIVE BUMP STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：用于半导体器件的导电保护结构及其制造方法
公开(公告)号：US20100297842A1
公开(公告)日：2010-11-25
申请号：US12851971
申请日：2010-08-06
申请人： Chun Chi KE , Chien-Ping HUANG , Don-Son JIUNG , Yu-Po WANG
发明人： Chun Chi KE , Chien-Ping HUANG , Don-Son JIUNG , Yu-Po WANG
IPC分类号： H01L21/60
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/0508 , H01L2224/05124 , H01L2224/05155 , H01L2224/05548 , H01L2224/05567 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/1134 , H01L2224/1147 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/1357 , H01L2224/136 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/13099
摘要： A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump.
摘要翻译：提供了一种用于半导体器件的导电凸块结构及其制造方法。金属凸块形成在电连接到半导体器件的连接焊盘上并形成在半导体器件的连接焊盘上的凸块下冶金（UBM）结构上，其中金属凸块的尺寸小于UBM结构。随后，在UBM结构上安装焊料凸点并封装金属凸块，以便增加接合面积，并同时允许焊料凸块在UBM结构上充分润湿以增强焊料凸块的粘结应力。

10. 发明授权

US07804173B2 Semiconductor device having conductive bumps and deviated solder pad 有权
标题翻译：具有导电凸块和偏移焊盘的半导体器件
公开(公告)号：US07804173B2
公开(公告)日：2010-09-28
申请号：US12005764
申请日：2007-12-27
申请人： Chun-Chi Ke , Chien-Ping Huang
发明人： Chun-Chi Ke , Chien-Ping Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05558 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13006 , H01L2224/13007 , H01L2224/13013 , H01L2224/13022 , H01L2224/13027 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/136 , H01L2224/14104 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/05552 , H01L2924/00 , H01L2924/00012 , H01L2924/013
摘要： A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.
摘要翻译：提供了具有导电凸块的半导体器件及其制造方法。该制造方法主要包括以下步骤：提供具有焊料焊盘和形成在其上的钝化层的半导体衬底，其中一部分焊料焊盘从钝化层暴露出来; 在焊料焊盘上设置第一金属层和围绕焊盘的钝化层的一部分; 在所述第一金属层和所述钝化层上设置覆盖层，以及在所述覆盖层中形成孔以暴露所述第一金属层的一部分，其中所述孔的中心偏离所述焊盘的中心; 在所述第一金属层的所述部分上沉积金属柱; 并在金属柱的外表面上沉积焊料，以提供更好的缓冲效果。

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