会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Fabrication method of multi-chip stack structure
    • 多芯片堆叠结构的制作方法
    • US07981729B2
    • 2011-07-19
    • US12818701
    • 2010-06-18
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • H01L21/60
    • H01L23/49575H01L24/45H01L24/48H01L24/49H01L24/78H01L24/85H01L25/50H01L2224/45144H01L2224/48091H01L2224/48247H01L2224/48465H01L2224/48496H01L2224/49175H01L2224/78H01L2224/85001H01L2924/00014H01L2924/01033H01L2924/01079H01L2924/01082H01L2924/014H01L2924/00
    • A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
    • 提出了一种多芯片堆叠结构及其制造方法,包括提供具有芯片基底和多个引线的引线框架,并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上,第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺,以通过多个第一接合线将第一芯片电连接到引线,以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中,通过凸块将引线框倒置放置到加热块, 以及执行第二引线接合处理,以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度,以便使接合线不会接触加热块,并且在现有技术的第二引线接合过程中不需要使用第二加热块,从而节省了时间和成本 在制造过程中。 此外,由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应,可以防止电性能和电不匹配受到不利影响的常规问题。
    • 6. 发明申请
    • FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE
    • 多芯片堆叠结构的制作方法
    • US20100255635A1
    • 2010-10-07
    • US12818701
    • 2010-06-18
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • H01L21/60
    • H01L23/49575H01L24/45H01L24/48H01L24/49H01L24/78H01L24/85H01L25/50H01L2224/45144H01L2224/48091H01L2224/48247H01L2224/48465H01L2224/48496H01L2224/49175H01L2224/78H01L2224/85001H01L2924/00014H01L2924/01033H01L2924/01079H01L2924/01082H01L2924/014H01L2924/00
    • A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
    • 提出了一种多芯片堆叠结构及其制造方法,包括提供具有芯片基底和多个引线的引线框架,并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上,第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺,以通过多个第一接合线将第一芯片电连接到引线,以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中,通过凸块将引线框倒置放置到加热块, 以及执行第二引线接合处理,以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度,以便使接合线不会接触加热块,并且在现有技术的第二引线接合过程中不需要使用第二加热块,从而节省了时间和成本 在制造过程中。 此外,由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应,可以防止电性能和电不匹配受到不利影响的常规问题。
    • 9. 发明申请
    • Multi-chip stack structure and fabrication method thereof
    • 多芯片堆叠结构及其制造方法
    • US20080224289A1
    • 2008-09-18
    • US12077003
    • 2008-03-13
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • Jung-Pin HuangChin-Huang ChangChien-Ping HuangChung-Lun LiuCheng-Hsu Hsiao
    • H01L23/495H01L21/00
    • H01L23/49575H01L24/45H01L24/48H01L24/49H01L24/78H01L24/85H01L25/50H01L2224/45144H01L2224/48091H01L2224/48247H01L2224/48465H01L2224/48496H01L2224/49175H01L2224/78H01L2224/85001H01L2924/00014H01L2924/01033H01L2924/01079H01L2924/01082H01L2924/014H01L2924/00
    • A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
    • 提出了一种多芯片堆叠结构及其制造方法,包括提供具有芯片基底和多个引线的引线框架,并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上,第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺,以通过多个第一接合线将第一芯片电连接到引线,以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中,通过凸块将引线框倒置放置到加热块, 以及执行第二引线接合处理,以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度,以便使接合线不会接触加热块,并且在现有技术的第二引线接合过程中不需要使用第二加热块,从而节省了时间和成本 在制造过程中。 此外,由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应,可以防止电性能和电不匹配受到不利影响的常规问题。