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1. 发明申请

US20090294959A1 Semiconductor package device, semiconductor package structure, and fabrication methods thereof 有权
标题翻译：半导体封装器件，半导体封装结构及其制造方法
公开(公告)号：US20090294959A1
公开(公告)日：2009-12-03
申请号：US12315787
申请日：2008-12-04
申请人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
发明人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
IPC分类号： H01L23/522 , H01L23/532 , H01L23/28 , H01L23/31
CPC分类号： H01L23/4334 , H01L21/486 , H01L23/31 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/00 , H01L2224/81
摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要翻译：提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料碰撞，切割晶片难度大。

2. 发明授权

US08304891B2 Semiconductor package device, semiconductor package structure, and fabrication methods thereof 有权
标题翻译：半导体封装器件，半导体封装结构及其制造方法
公开(公告)号：US08304891B2
公开(公告)日：2012-11-06
申请号：US12315787
申请日：2008-12-04
申请人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
发明人： Cheng-Chia Chiang , Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Jung-Pin Huang
IPC分类号： H01L23/28 , H01L23/31 , H01L23/52 , H01L23/00
CPC分类号： H01L23/4334 , H01L21/486 , H01L23/31 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/00 , H01L2224/81
摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要翻译：提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料碰撞，切割晶片难度大。

3. 发明申请

US20080258306A1 Semiconductor Device and Method for Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080258306A1
公开(公告)日：2008-10-23
申请号：US12105538
申请日：2008-04-18
申请人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
发明人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02371 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/48091 , H01L2224/82001 , H01L2224/97 , H01L2225/06562 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2224/82 , H01L2924/01028 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。

4. 发明授权

US07981729B2 Fabrication method of multi-chip stack structure 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US07981729B2
公开(公告)日：2011-07-19
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

5. 发明申请

US20110227226A1 MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA 审中-公开
标题翻译：通过硅的多芯片堆叠结构
公开(公告)号：US20110227226A1
公开(公告)日：2011-09-22
申请号：US13151823
申请日：2011-06-02
申请人： Chiang-Cheng Chiang , Chien-Ping Huang , Chin-Huang Chang , Chi-Hsin Chiu , Jung-Pin Huang
发明人： Chiang-Cheng Chiang , Chien-Ping Huang , Chin-Huang Chang , Chi-Hsin Chiu , Jung-Pin Huang
IPC分类号： H01L23/48
CPC分类号： H01L29/0657 , H01L23/481 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05023 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/14181 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01079 , H01L2224/81 , H01L2924/00012 , H01L2224/05599
摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.
摘要翻译：本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

6. 发明申请

US20100255635A1 FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20100255635A1
公开(公告)日：2010-10-07
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

7. 发明申请

US20090032928A1 Multi-chip stack structure having through silicon via and method for fabrication the same 审中-公开
标题翻译：具有硅通孔的多芯片堆叠结构及其制造方法
公开(公告)号：US20090032928A1
公开(公告)日：2009-02-05
申请号：US12220995
申请日：2008-07-30
申请人： Chiang-Cheng Chiang , Chien-Ping Huang , Chin-Huang Chang , Chi-Hsin Chiu , Jung-Pin Huang
发明人： Chiang-Cheng Chiang , Chien-Ping Huang , Chin-Huang Chang , Chi-Hsin Chiu , Jung-Pin Huang
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L29/0657 , H01L23/481 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05023 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/14181 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01079 , H01L2224/81 , H01L2924/00012 , H01L2224/05599
摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.
摘要翻译：本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

8. 发明申请

US20080283994A1 Stacked package structure and fabrication method thereof 审中-公开
标题翻译：堆叠封装结构及其制造方法
公开(公告)号：US20080283994A1
公开(公告)日：2008-11-20
申请号：US12152687
申请日：2008-05-16
申请人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
发明人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/49 , H01L21/56
CPC分类号： H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/1134 , H01L2224/1308 , H01L2224/1411 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/3436 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.
摘要翻译：公开了一种堆叠封装结构及其制造方法，包括提供一种具有形成在其表面上的多个可叠置焊料焊盘的衬底，用于允许至少一个半导体芯片电连接到衬底; 形成用于封装半导体芯片的密封剂，并进一步从可密封剂暴露可堆叠的焊盘，从而形成下层半导体封装; 通过引线接合在至少一个可堆叠的焊盘上形成导电凸块，使得至少一个上层半导体封装可以经由焊球安装在导电凸块和下层半导体封装的可堆叠焊盘上，以形成堆叠的封装结构，其中，焊球和导电凸块的堆叠高度大于下层半导体封装的密封剂的高度，因此，当堆叠精细间距半导体封装时或当上行半导体封装发生翘曲时或下层半导体封装，导电凸块可以补偿由焊球塌陷引起的不适当的高度，或填充由经线引起的焊球和可堆叠焊盘之间的间隙，从而允许焊球能够有效地接触和在下层半导体封装的衬底上湿润。

9. 发明申请

US20080224289A1 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

10. 外观设计

USD493799S1 Digital memory card 失效
标题翻译：数码存储卡
公开(公告)号：USD493799S1
公开(公告)日：2004-08-03
申请号：US29195995
申请日：2003-12-18
申请人： Cheng-Chia Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai
设计人： Cheng-Chia Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai

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