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1. 发明申请

US20030022504A1 Toxic residual gas removal by non-reactive ion sputtering 失效
标题翻译：通过非反应性离子溅射去除有毒残留气体
公开(公告)号：US20030022504A1
公开(公告)日：2003-01-30
申请号：US09912623
申请日：2001-07-25
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Zou Zheng , Zhou Mei Sheng , Yelehanka Ramachandramurthy Pradeep , Paul Proctor
IPC分类号： H01L021/311
CPC分类号： H01L21/3065
摘要： A novel method to remove residual toxic gases trapped by a polymerizing process by an inert ion sputter is described. A masking layer is formed overlying a semiconductor substrate. An opening is etched through the masking layer into the semiconductor substrate whereby a polymer forms on sidewalls of the opening and whereby residual toxic gas reactants from gases used in the etching step are adsorbed by the polymer. Thereafter, the polymer is sputtered with non-reactive ions whereby the residual toxic gas reactants are desorbed from the polymer to complete removal of residual toxic gas reactants in the fabrication of an integrated circuit device.
摘要翻译：描述了通过惰性离子溅射去除由聚合方法捕获的残余有毒气体的新方法。掩模层形成在半导体衬底上。通过掩模层将开口蚀刻到半导体衬底中，由此在开口的侧壁上形成聚合物，由此在蚀刻步骤中使用的来自气体的残留的有毒气体反应物被聚合物吸附。此后，用非反应性离子溅射聚合物，由此残留的有毒气体反应物从聚合物中脱附，以在集成电路器件的制造中完全去除残余的有毒气体反应物。

2. 发明申请

US20040004054A1 Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits 失效
标题翻译：在同一电介质区域上形成高k和低k材料的方法及其在混合模式电路中的应用
公开(公告)号：US20040004054A1
公开(公告)日：2004-01-08
申请号：US10189876
申请日：2002-07-05
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Yelehanka Ramachandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Purakh Verma
IPC分类号： H01B013/00
CPC分类号： H01L28/55 , H01L21/02109 , H01L21/3127 , H01L21/3144 , H01L21/31625 , H01L21/31629 , H01L27/0617 , H01L27/0629 , H01L27/1203 , H01L2924/0002 , Y10T428/12035 , H01L2924/00
摘要： A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a a layer of choice.
摘要翻译：一种提供用于在具有高和低介电常数的半导体材料的一个平面层中形成的新方法。具有选择且优选不相同的介电常数参数的层被依次沉积，散布有蚀刻停止材料层。这些层可以被蚀刻，在那里形成开口，通过这些层可以填充一层选择。

3. 发明申请

US20020173106A1 Method for forming variable-K gate dielectric 失效
公开(公告)号：US20020173106A1
公开(公告)日：2002-11-21
申请号：US10196111
申请日：2002-07-16
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L021/336 , H01L021/31 , H01L021/469
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

4. 发明申请

US20020098655A1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
公开(公告)号：US20020098655A1
公开(公告)日：2002-07-25
申请号：US09765040
申请日：2001-01-19
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L021/00 , H01L021/84 , H01L021/8238 , H01L021/336 , H01L021/20
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

5. 发明申请

US20040016881A1 Image compensation device for a scanning electron microscope 有权
标题翻译：用于扫描电子显微镜的图像补偿装置
公开(公告)号：US20040016881A1
公开(公告)日：2004-01-29
申请号：US10207551
申请日：2002-07-29
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Kevin Chan Ee Peng , Yelehanka Ramachandramurthy Pradeep , Chua Thow Phock
IPC分类号： H01J037/256
CPC分类号： H01J37/09 , H01J2237/28
摘要： An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electromagnetic emissions generated by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.
摘要翻译：一种用于在由相邻制造设备产生的外部电磁辐射的影响下由SEM形成的关键尺寸线图像的变形的装置。外部发射导致高三西格玛A / C分量。校正装置包括安装在扫描电镜的柱壳体上的外部屏蔽线圈。控制发光驱动器安装到外部屏蔽线圈，其中具有变压器的可变分压器具有可变电阻器。调节可变电阻器改变A / C信号的正弦波的振幅，从而控制电发射驱动器，同时减少三西格玛A / C分量的影响。

6. 发明申请

US20020102798A1 METHOD FOR FABRICATING A SELF ALIGNED S/D CMOS DEVICE ON INSULATED LAYER BY FORMING A TRENCH ALONG THE STI AND FILL WITH OXIDE 失效
标题翻译：在绝缘层上制造自对准的S / D CMOS器件的方法，通过在氧化物上形成铁素体和填充物
公开(公告)号：US20020102798A1
公开(公告)日：2002-08-01
申请号：US09769830
申请日：2001-01-26
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L021/336 , H01L021/76
CPC分类号： H01L29/6653 , H01L21/76232 , H01L21/823814 , H01L21/823878 , H01L29/41783 , H01L29/456 , H01L29/66636
摘要： A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.
摘要翻译：一种通过在STI侧面形成沟槽并用氧化物填充沟槽，在绝缘层（氧化物）上具有升高的源极/漏极（S / D）区域的自对准TX的方法。 STI区域形成在基板中。形成栅极结构。在基板中与栅极结构相邻地形成LDD区域。隔板形成在栅极结构的侧壁上。我们蚀刻STI区域和第一间隔物之间的S / D沟槽。 S / D沟槽填充有S / D绝缘层。在S / D绝缘层和LDD区域上形成升高的S / D区域。在STI区域上形成顶部隔离层。本发明在绝缘层上构建了凸起的源极/漏极（S / D）区域，并减少了结合漏电和热载流子对栅极氧化物的降解。

7. 发明申请

US20020076877A1 Method to form self-aligned, L-shaped sidewall spacers 审中-公开
公开(公告)号：US20020076877A1
公开(公告)日：2002-06-20
申请号：US10077093
申请日：2002-02-19
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： Subhash Gupta , Yelehanka Ramachandramurthy Pradeep , Vijai Kumar Chhagan
IPC分类号： H01L021/338 , H01L021/8238
CPC分类号： H01L29/6659 , H01L21/31116 , H01L21/823468
摘要： A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer. The silicon nitride layer is anisotropically etched to form silicon nitride sidewall spacers with an L-shaped profile. The integrated circuit device is completed.

8. 发明申请

US20040023506A1 Method of blocking nitrogen from thick gate oxide during dual gate CMP 失效
标题翻译：在双栅极CMP期间从厚栅极氧化物阻挡氮的方法
公开(公告)号：US20040023506A1
公开(公告)日：2004-02-05
申请号：US10209151
申请日：2002-07-30
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Yelehanka Ramachandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Purakh Verma
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/823857 , H01L21/3144
摘要： In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.
摘要翻译：根据本发明的目的，提供了一种用于产生具有不等厚度的栅极氧化物层的新方法。活性表面区域限定在衬底的表面上，在活性表面上生长厚的栅极氧化物层。选择性蚀刻被施加到栅极氧化物的厚层，选择性地将栅极氧化物的厚层的厚度减小到栅极氧化物的薄层所需的厚度。厚栅氧化物层被遮挡。将N2原子注入到氧化物薄层的暴露表面中，进行快速热处理，并从栅极氧化物的厚层的表面去除阻挡掩模。现在在栅极氧化物的薄层中提供了高浓度的氮化物。

9. 发明申请

US20030203710A1 Linear polishing for improving substrate uniformity 失效
标题翻译：线性抛光，提高基体均匀性
公开(公告)号：US20030203710A1
公开(公告)日：2003-10-30
申请号：US10134821
申请日：2002-04-26
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Subramanian Balakumar , Chen Feng , Victor Seng-Keong Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B007/22
CPC分类号： B24B37/16 , B24B21/10 , B24B37/245
摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
摘要翻译：一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。每个带具有外部抛光表面和内部光滑表面带彼此沿着彼此间隔开，在每一端共享公共轴线。皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。压板构件插入每个带并且放置在成对的辊之间。压板提供抛光平面和抛光带的支撑表面。抛光平面包括与平面下方的细长的增压室连通的多个孔。该室供应压缩气体以向抛光带施加向上的压力。驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

10. 发明申请

US20030017710A1 Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area 审中-公开
标题翻译：通过形成用于I / O或闭锁敏感区域的选择性倾斜楼梯STI结构来提高闩锁的方法
公开(公告)号：US20030017710A1
公开(公告)日：2003-01-23
申请号：US09907649
申请日：2001-07-19
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Pan Yang , James Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan
IPC分类号： C23F001/00 , C03C015/00 , H01L021/461
CPC分类号： H01L21/823878 , H01L21/76232 , H01L27/0921
摘要： A method of forming a sloped staircase STI structure, comprising the following steps. a) A substrate having an upper surface is provided. b) A patterned masking layer is formed over the substrate to define an STI region. The patterned masking layer having exposed sidewalls. c) The substrate is etched a first time through the masking layer to form a first step trench within the STI region. The first step trench having exposed sidewalls. d) Continuous side wall spacers are formed on the exposed patterned masking layer and first step trench sidewalls. e) The substrate is etched a second time using the masking layer and the continuous sidewall spacers as masks to form a second step trench within the STI region. The second step trench having exposed sidewalls. f) Second side wall spacers are formed on the second step trench sidewalls. g) Steps e) and f) are repeated x more times to create xnull2 total step trenches and xnull2 total side wall spacers on xnull2 total step trench sidewalls. h) A planarized STI is formed within the STI region substantially level with the substrate upper surface and over the xnull2 total step trenches.
摘要翻译：一种形成倾斜楼梯STI结构的方法，包括以下步骤。 a）提供具有上表面的基板。 b）在衬底上形成图案化掩模层以限定STI区域。图案化掩模层具有暴露的侧壁。 c）首先通过掩模层蚀刻衬底，以在STI区域内形成第一阶跃沟槽。第一级沟槽具有暴露的侧壁。 d）连续的侧壁间隔物形成在暴露的图案化掩模层和第一阶梯沟侧壁上。 e）使用掩模层和连续的侧壁间隔物作为掩模第二次蚀刻基板，以在STI区域内形成第二阶跃沟槽。第二级沟槽具有暴露的侧壁。 f）第二侧壁间隔物形成在第二台阶沟槽侧壁上。 g）步骤e）和f）重复x次以在x + 2个总阶梯形沟槽侧壁上产生x + 2个总台阶沟槽和x + 2个总侧壁间隔物。 h）在STI区域内形成平坦化STI，其基本上与衬底上表面平齐，并且在x + 2个总步进沟槽上。

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