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1. 发明申请

US20030148617A1 METHOD OF FORMING SMALL TRANSISTOR GATES BY USING SELF-ALIGNED REVERSE SPACER AS A HARD MASK 有权
标题翻译：通过使用自对准的反向间隔器作为硬掩模形成小晶闸管的方法
公开(公告)号：US20030148617A1
公开(公告)日：2003-08-07
申请号：US10068053
申请日：2002-02-05
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Chew-Hoe Ang , Eng-Hua Lim , Randall Cha , Jia-Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L021/311
CPC分类号： H01L21/28132
摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
摘要翻译：一种形成窄门的方法，包括以下步骤。提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。栅极材料层形成在栅极介电层上。在栅极材料层上形成硬掩模层。图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。形成围绕硬掩模/栅极材料层叠层的平坦化介电层。图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。去除平坦化的介电层。去除掩模间隔物以形成包括栅极材料的窄门。

2. 发明申请

US20020102798A1 METHOD FOR FABRICATING A SELF ALIGNED S/D CMOS DEVICE ON INSULATED LAYER BY FORMING A TRENCH ALONG THE STI AND FILL WITH OXIDE 失效
标题翻译：在绝缘层上制造自对准的S / D CMOS器件的方法，通过在氧化物上形成铁素体和填充物
公开(公告)号：US20020102798A1
公开(公告)日：2002-08-01
申请号：US09769830
申请日：2001-01-26
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L021/336 , H01L021/76
CPC分类号： H01L29/6653 , H01L21/76232 , H01L21/823814 , H01L21/823878 , H01L29/41783 , H01L29/456 , H01L29/66636
摘要： A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.
摘要翻译：一种通过在STI侧面形成沟槽并用氧化物填充沟槽，在绝缘层（氧化物）上具有升高的源极/漏极（S / D）区域的自对准TX的方法。 STI区域形成在基板中。形成栅极结构。在基板中与栅极结构相邻地形成LDD区域。隔板形成在栅极结构的侧壁上。我们蚀刻STI区域和第一间隔物之间的S / D沟槽。 S / D沟槽填充有S / D绝缘层。在S / D绝缘层和LDD区域上形成升高的S / D区域。在STI区域上形成顶部隔离层。本发明在绝缘层上构建了凸起的源极/漏极（S / D）区域，并减少了结合漏电和热载流子对栅极氧化物的降解。

3. 发明申请

US20040072435A1 Method of integrating L - shaped spacers in a high performance CMOS process via use of an oxide - nitride - doped oxide spacer 失效
标题翻译：通过使用氧化物 - 氮化物掺杂氧化物间隔物在高性能CMOS工艺中集成L形间隔物的方法
公开(公告)号：US20040072435A1
公开(公告)日：2004-04-15
申请号：US10267206
申请日：2002-10-09
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Elgin Quek
IPC分类号： H01L021/302 , H01L021/461 , H01L021/311
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A process for fabricating a complimentary metal oxide semiconductor (CMOS), device featuring composite insulator spacer shapes which allow P channel (PMOS), short channel effects to be minimized, and allow reductions in resistance for N channel (NMOS), source/drain extension regions to be realized, has been developed. The process features initial composite insulator spacers formed in the sides of gate structures after definition of the NMOS and PMOS source/drain extension regions. The initial composite insulator spacer, comprised of an underlying silicon oxide component, an L-shaped silicon nitride component, and an overlying doped oxide component, is then used for definition of the PMOS heavily doped source/drain region, allowing for adequate space between the heavily doped source/drain and channel regions, thus reducing the risk of short channel effects. After removal of the doped oxide component, the L-shaped composite insulator spacer is used to define, via ion implantation procedures, an NMOS heavily doped region, featuring a portion of the heavily doped source/drain region formed underlying a horizontal feature of the L-shaped silicon nitride component, therefore compensating a portion of the NMOS source/drain extension region, and resulting in the desired reduction in source/drain resistance.
摘要翻译：用于制造互补金属氧化物半导体（CMOS）的器件，其特征在于复合绝缘体间隔物形状，其允许P沟道（PMOS），短沟道效应被最小化，并且允许降低N沟道（NMOS）的电阻/源极/漏极扩展要实现的地区，已经开发。该工艺的特征在于限定NMOS和PMOS源极/漏极延伸区域之后，在栅极结构的侧面形成初始复合绝缘体间隔物。然后，使用包括下面的氧化硅组分，L型氮化硅组分和上覆的掺杂氧化物组分的初始复合绝缘体间隔物来定义PMOS重掺杂源极/漏极区域，从而允许在重掺杂的源极/漏极和沟道区域，从而降低短沟道效应的风险。在去除掺杂的氧化物组分之后，使用L形复合绝缘体间隔物来经由离子注入工艺来定义NMOS重掺杂区域，其特征在于在L的水平特征下形成的重掺杂源极/漏极区的一部分形状的氮化硅部件，因此补偿NMOS源极/漏极延伸区域的一部分，并导致所需的源极/漏极电阻的降低。

4. 发明申请

US20030022450A1 Method to form elevated source/drain using poly spacer 失效
标题翻译：使用聚间隔物形成升高的源极/漏极的方法
公开(公告)号：US20030022450A1
公开(公告)日：2003-01-30
申请号：US09912607
申请日：2001-07-25
申请人： Chartered Semiconductor manufacturing Ltd.
发明人： Yang Pan , James Lee Yong Meng , Leung Ying Keung , Yelehanka Ramachandramurthy Predeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundarensan
IPC分类号： H01L021/336 , H01L021/3205
CPC分类号： H01L29/6659 , H01L21/2257 , H01L29/41775 , H01L29/41783 , H01L29/665 , H01L29/6656
摘要： A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.
摘要翻译：描述了一种形成具有升高的源极/漏极结构的二分之一微米MOSFET的方法。在半导体衬底上的栅极电介质上形成栅电极。使用栅电极作为掩模将离子注入到半导体衬底中以形成轻掺杂区域。此后，在栅电极的侧壁上形成电介质间隔物。沉积覆盖半导体衬底，栅电极和电介质间隔物的多晶硅层，其中多晶硅层被重掺杂。蚀刻多晶硅层以在电介质间隔物上留下多晶硅间隔物。掺杂剂从多晶硅间隔物扩散到半导体衬底中以在多晶硅间隔物下面形成源极和漏极区域。去除栅电极端部上的多晶硅间隔物以将多晶硅间隔物分离成源多晶硅间隔物和漏极多晶硅间隔物，从而在集成电路器件的制造中完成形成具有升高的源极/漏极结构的MOSFET。

5. 发明申请

US20040157397A1 Method of forming a pocket implant region after formation of composite insulator spacers 有权
标题翻译：在形成复合绝缘垫片之后形成凹穴注入区域的方法
公开(公告)号：US20040157397A1
公开(公告)日：2004-08-12
申请号：US10361934
申请日：2003-02-10
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Elgin Quek
IPC分类号： H01L021/3205 , H01L021/336 , H01L021/4763
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.
摘要翻译：已经开发了用于形成MOSFET器件的工艺，其特征在于仅与重掺杂源极/漏极区域的侧面的顶部附近放置的口袋区域。该工艺的特征是在未被栅极结构覆盖的半导体衬底的区域中或通过位于栅极结构的侧面上的复合绝缘体间隔物形成重掺杂的源极/漏极区域。选择性去除复合绝缘体间隔物的上覆绝缘体部件允许随后的口袋注入区域形成在半导体衬底的直接位于剩余的L形绝缘体间隔件部件的水平部分下方的区域中。仅在重掺杂的源极/漏极区域形成对接的顶部的袋区域的位置降低穿通电流的风险，同时限制结电容的冲击。

6. 发明申请

US20020173106A1 Method for forming variable-K gate dielectric 失效
公开(公告)号：US20020173106A1
公开(公告)日：2002-11-21
申请号：US10196111
申请日：2002-07-16
申请人： CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L021/336 , H01L021/31 , H01L021/469
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

7. 发明申请

US20020098655A1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
公开(公告)号：US20020098655A1
公开(公告)日：2002-07-25
申请号：US09765040
申请日：2001-01-19
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L021/00 , H01L021/84 , H01L021/8238 , H01L021/336 , H01L021/20
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

8. 发明申请

US20040266155A1 Formation of small gates beyond lithographic limits 审中-公开
标题翻译：形成超过光刻极限的小门
公开(公告)号：US20040266155A1
公开(公告)日：2004-12-30
申请号：US10610047
申请日：2003-06-30
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Chew Hoe Ang , Eng Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei Sheng Zhou , Daniel Yen
IPC分类号： H01L021/4763 , H01L021/8242 , H01L021/336 , H01L021/3205
CPC分类号： H01L29/66553 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/31144 , H01L29/66583
摘要： A method of fabricating an ultra-small semiconductor structure comprising the following steps. A substrate having a lower dielectric layer and an overlying upper dielectric layer formed thereover is provided. Using a lithography process having a lithography limit, the upper dielectric layer is patterned to form a first opening exposing a portion of the lower dielectric layer. The first opening having exposed side walls and a width equal to the lithography limit. Sidewall spacers having a lower width are formed over the exposed side walls of the first opening. Using the sidewall spacers as masks, the lower dielectric layer is patterned to form a lower opening having a width less than the first opening width. The patterned upper dielectric layer is removed. An ultra-small semiconductor structure is formed within the lower opening. The ultra-small semiconductor structure having a width equal to the lithography limit minus twice the lower width of the sidewall spacer.
摘要翻译：一种制造超小型半导体结构的方法，包括以下步骤。提供具有下介电层和形成在其上的上覆盖层的基板。使用具有光刻极限的光刻工艺，将上电介质层图案化以形成露出下介电层的一部分的第一开口。第一开口具有暴露的侧壁和宽度等于光刻极限。在第一开口的暴露的侧壁上形成具有较低宽度的侧壁间隔物。使用侧壁间隔件作为掩模，下电介质层被图案化以形成具有小于第一开口宽度的宽度的下开口。去除图案化的上介电层。在下开口内形成有超小型半导体结构。具有等于光刻极限的宽度减去侧壁间隔物的较低宽度的两倍的超小半导体结构。

9. 发明申请

US20040164320A1 Method of activating polysilicon gate structure dopants after offset spacer deposition 失效
标题翻译：在偏移间隔物沉积后激活多晶硅栅极结构掺杂剂的方法
公开(公告)号：US20040164320A1
公开(公告)日：2004-08-26
申请号：US10361877
申请日：2003-02-10
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Elgin Quek , Francis Benistant
IPC分类号： H01L031/0328
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A process sequence used to integrate an anneal cycle, used to activate ion implanted dopants in a polysilicon gate structure, and the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure, has been developed. The process sequence features ion implantation of dopants into a blanket polysilicon layer located overlying a metal oxide semiconductor field effect transistor (MOSFET), gate insulator layer. After definition of the polysilicon gate structure a silicon oxide layer is deposited, followed by an anneal procedure allowing activation of the implanted dopants in the polysilicon gate structure to occur. Out diffusion of implanted dopants during the activation anneal procedure is minimized as a result of the overlying silicon oxide layer. An anisotropic dry etching procedure is then performed on the silicon oxide layer resulting in the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure.
摘要翻译：已经开发了用于整合用于激活多晶硅栅极结构中的离子注入掺杂剂的退火循环的处理顺序以及多晶硅栅极结构侧面上的偏移氧化硅间隔物的定义。工艺顺序的特征是将掺杂剂离子注入位于覆盖金属氧化物半导体场效应晶体管（MOSFET）栅极绝缘体层的覆盖多晶硅层中。在多晶硅栅极结构的定义之后，沉积氧化硅层，随后进行退火程序，允许在多晶硅栅极结构中激发注入的掺杂剂。在激活退火过程中注入的掺杂剂的扩散由于上覆的氧化硅层而被最小化。然后在氧化硅层上进行各向异性的干法蚀刻，得到多晶硅栅极结构侧面的偏移氧化硅间隔物的定义。

10. 发明申请

US20040132271A1 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing 有权
标题翻译：用于使用溅射金属沉积，金属离子注入或硅注入的CMOS器件和激光退火的双栅极（一个金属和一个多晶硅或金属硅化物）的制造方法
公开(公告)号：US20040132271A1
公开(公告)日：2004-07-08
申请号：US10338156
申请日：2003-01-08
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L021/8238 , H01L021/4763 , H01L021/3205
CPC分类号： H01L29/4933 , H01L21/268 , H01L21/28061 , H01L21/823842
摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
摘要翻译：一种制造第一和第二栅极的方法，包括以下步骤。提供了其上形成有栅介电层的基板。衬底具有第一栅极区域和第二栅极区域。在栅极电介质层上形成薄的第一栅极层。第二栅极区域内的薄的第一栅极层被掩蔽以暴露第一栅极区域内的薄的第一栅极层的一部分。薄的第一栅极层的暴露部分被转换成薄的第三栅极层部分。在薄的第一和第三栅极层部分上形成第二栅极层。第二栅极层和第一和第三栅极层部分被图案化以在第一栅极区域内形成第一栅极，在第二栅极区域内形成第二栅极。

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