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1. 发明申请

US20040087101A1 High K artificial lattices for capacitor applications to use in CU or AL BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于CU或AL BEOL
公开(公告)号：US20040087101A1
公开(公告)日：2004-05-06
申请号：US10286627
申请日：2002-11-02
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L021/20 , H01L021/8242 , H01L021/4763
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4 , 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process
摘要翻译：一种制造高介电常数MIM电容器的改进和新工艺。这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。对于高介电常数MIM电容器，金属在双镶嵌工艺中由铜电极组成。超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。因此，可以容易地控制膜的厚度。介电常数的增强是由于界面。接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程

2. 发明申请

US20030203710A1 Linear polishing for improving substrate uniformity 失效
标题翻译：线性抛光，提高基体均匀性
公开(公告)号：US20030203710A1
公开(公告)日：2003-10-30
申请号：US10134821
申请日：2002-04-26
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Subramanian Balakumar , Chen Feng , Victor Seng-Keong Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B007/22
CPC分类号： B24B37/16 , B24B21/10 , B24B37/245
摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
摘要翻译：一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。每个带具有外部抛光表面和内部光滑表面带彼此沿着彼此间隔开，在每一端共享公共轴线。皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。压板构件插入每个带并且放置在成对的辊之间。压板提供抛光平面和抛光带的支撑表面。抛光平面包括与平面下方的细长的增压室连通的多个孔。该室供应压缩气体以向抛光带施加向上的压力。驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

3. 发明申请

US20030148712A1 Multiple step CMP polishing 失效
标题翻译：多步CMP抛光
公开(公告)号：US20030148712A1
公开(公告)日：2003-08-07
申请号：US10062656
申请日：2002-02-01
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Victor Seng-Keong Lim , Chen Feng , Subramanian Balakumar , Paul Proctor
IPC分类号： B24B001/00
CPC分类号： B24B37/26 , B24B57/02
摘要： An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste.
摘要翻译：一种用于平坦化半导体表面材料的改进的化学机械抛光装置。具有常规CMP工艺的附接垫的单个旋转抛光平台被两个受控的独立驱动的同心和共面的抛光平台替代。两个共面抛光平台允许CMP抛光过程的单独可调选项。这些选项通过具有不同材料组成和硬度的垫来提供。此外，在压板之间提供环形空间，以在相同的CMP工具上引入两个浆料配方的使用，一个对每个垫。压板之间的环形空间形成用于捕获和包含废料的排水路径。

4. 发明申请

US20030003745A1 New method for improving oxide erosion of tungsten CMP operations 有权
标题翻译：改善钨CMP操作的氧化物侵蚀的新方法
公开(公告)号：US20030003745A1
公开(公告)日：2003-01-02
申请号：US09893080
申请日：2001-06-28
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Xian Bin Wang , Yi Xu , Subramanian Balakumar , Cuiyang Wang
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在氧化物上使用氮化硅层来防止金属塞过程中的氧化物侵蚀的新方法。沉积在半导体衬底上的氧化物层。沉积氮化硅层覆盖氧化物层。通过氮化硅层蚀刻开口并进入氧化物层。在氮化硅层上沉积阻挡金属层并进入开口。沉积在阻挡金属层上的金属层。使用化学机械抛光（CMP）在氮化硅层上抛光停止来抛光金属层和阻挡金属层。金属层形成金属塞。氮化硅层在抛光步骤期间防止氧化物层的侵蚀，以在集成电路器件的制造中完成金属插塞的形成。

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